參數(shù)資料
型號(hào): HMS91C8032
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, MQFP-80
文件頁數(shù): 77/90頁
文件大小: 1557K
代理商: HMS91C8032
HMS9xC7132 / HMS9xC7134
May.2001 ver1.1
73
21. OPERATION MODE
21.1 OTP MODE
The HMS97C7132 is programmed by using a modified Quick-
Pulse Programming algorithm. The HMS97C7132 contains two
signature bytes that can be read and used by an EPROM program-
ming system to identify the device. The signature bytes identify
the device as an manufactured by HME. Table 21-1 shows the
logic levels for reading the signature byte, and for programming
the program memory, the encryption table, and the security bits.
The circuit configuration and waveforms for quick pulse pro-
gramming are shown in Figure 21-1 and Figure 21-2. Figure 21-
3 shows the circuit configuration for normal program memory
verification.
Program / Verify algorithms
Any algorithm in agreement with the conditions listed in Table 21-1, and which satisfies the timing specifications is suitable.
Table 21-1 EPROM programming modes
Note :
1. “0” = Valid low for that pin, “1”= Valid high for that pin.
2. VPP = 12.75V 0.25V
3. VDD = 5V
10% during programming and verification.
4. P3.5/PROG receives 10 programming pulses while VPP is held at 12.75V.
Each programming pulse is low for 100
(
10
) and high for a minimum of 10
Program Memory Lock Bits
The two-level Program Lock system consists of 2 Lock Bits and a 64-bytes Encryption Array which are used to protect the program mem-
ory against software piracy.
Table 21-2Lock Bit Protection Modes
Read Signature
Verify Code Data
Program Code Data
Program Encryption Table
Program Lock Bit 1
Program Lock Bit 2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
VPP
VPP
VPP
VPP
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
MODE
RESET
P3.3
P3.5/
PROG
INT0/
VPP
P2.7
P2.6
P3.7
P3.6
P3.2
1
1
1
1
1
1
U : unprogrammed, P : programmed
LB2
Protection Type
U
No program lock features
U
Further programming of the EPROM is disabled
LB1
U
P
P
P
Same as mode 2, also verify is disabled
MODE
1
2
3
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