參數(shù)資料
型號: HMS91C8032
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝: PLASTIC, MQFP-80
文件頁數(shù): 46/90頁
文件大?。?/td> 1557K
代理商: HMS91C8032
HMS9xC7132 / HMS9xC7134
42
May.2001 ver1.1
16. DDC INTERFACE
The monitor typically includes a number of user controls to set
picture size, position, color balance, brightness and contrast.Fur-
thermore, to optimize some internal setting for different display
modes, the timing characteristics should be acquired by the con-
trol side. In these days, it is getting popular for these controls to
go to PC host. Therefore the communication between monitor
and host becomes issue.DDC1, DDC2B, DDC2B+, and
DDC2AB(ACCESS.bus) emerge as a standard for monitor inter-
face. A transmitter clocked by incoming VSYNC is dedicated for
DDC1 operation. An I2C interface hardware logic forms the ker-
nel of DDC2B, DDC2B+, and DDC2AB. An address pointer,
with post increment capability is employed to serve DDC1,
DDC2B,DDC2B+ and DDC2AB modes.
The conceptual block diagram is illustrated in Fig. 16.1
Figure 16-1 DDC Interface block diagram
DDC2B/DDC2AB
DDC2B+ Interface
S1ADR1
S1DAT
S1CON
S1STA
SDA1
SCL1
DDCCON
VSYNC
IN
INTR (From S1STA)
INT
DDCADR
DDCDAT
X
EX_
DAT
SW
ENB
X
DDC1
INT
DDC1
EN
SWH
INT
M0
Initialization synchronization
DDC1 transmitter
DDC1 Hold Register
Bus Clock Generator
Shift Register
Monitor Address
Arbitration Logic
DDC1/DDC2
Detection
RAMBUF
RAM
Buffer
Address Pointer
I
S1ADR0
7
1
0
Monitor Address
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