參數(shù)資料
型號(hào)： HMS91C8032
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, MQFP-80
文件頁(yè)數(shù)： 50/90頁(yè)
文件大?。?/td> 1557K
代理商： HMS91C8032
HMS9xC7132 / HMS9xC7134
46
May.2001 ver1.1
16.2 DDC1 protocol
DDC1 is primitive and a point to point interface. The monitor is
always put at “Transmit only” mode.In the initialization phase, 9
clock cycles on VSYNC pin will be given for the internal syn-
chronization.During this period, the SDA pin will be kept at high
impedance state.
If DDC1 hardware mode is used, the following procedure is rec-
ommended to proceed DDC1 operation.
Step1 : Reset DDC1EN (by default, DDC1EN is cleared as low
after power on reset).
Step2 : Set SWENB as high(the default value is zero.)
Step3 : Depending on the data size of EDID data, set EX_DAT
as low(128 bytes) or high(256bytes).
Step4 : By using bulky moving commands (DDCADR, RAM-
BUF involved) to move the entire EDID data to RAM buffer.
Step5 : Reset SWENB to low.
Step6 : Reset DDCADR to 00H.
Step7 : Set DDC1EN as high.
In case SWENB is set as high, interrupt service routine must be
finished within 40 machine cycles in 12 MHz system clock.
Note : If EX_DAT equals to low, it is meant the lower part is oc-
cupied by DDC1 operation and the upper part is still free to
the system. Nevertheless, the effect of the post increment just ap-
plies to the part related to DDC1 operation.
In other words, the system program is still able to address the lo-
cations from 128 to 255 in the RAM buffer through MOVX com-
mand but without the facility of the post increment.
ex) In case of accessing 200 of the RAM Buffer.
MOV R0, #200
MOVX A, @R0
Figure 16-3 Transmission protocol in DDC1 interface.
16.3 DDC2B protocol
DDC2B is constructed base on Philips I2C interface. However, in
the level of DDC2B, PC host is fixed as the master and the mon-
itor is always regarded as the slave. Both master and slave can be
operated as a transmitter or receiver, but the master device deter-
mines which mode is activated. In this protocol, address pointer
is also used.
According to DDC2B specification, A0(for write mode) and
A1(for read mode) are assigned as the default address of moni-
tors.
The reception of the incoming data in write mode or the updating
of the outgoing data in read mode should be finished within the
specified time limit. If software in the slave s side cannot react to
the master in time, based on I2C protocol, SCL pin can be
stretched low to inhibit the further action from the master. The
transaction can be proceeded in either byte or burst format.
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
B7 B6 B5 B4
B3 B2 B1 B0 HiZ B7
t
SU(DDC1)
t
DOV
Hi-Z
SCL
VCLK
DDC1INT
DDC1EN
SDA
t
H(VSYNC)
t
L(VSYNC)
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