參數(shù)資料
型號(hào)： HMS91C8032
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, MQFP-80
文件頁(yè)數(shù)： 64/90頁(yè)
文件大?。?/td> 1557K
代理商： HMS91C8032
HMS9xC7132 / HMS9xC7134
60
May.2001 ver1.1
19. SYNC PROCESSOR
The characteristics of Sync processor are as follows.
Automatic mode detection by hardware to capture the following signal characteristics :
Hsync and Vsync frequency measured with 12-bit accuracy (fSH= 12MHz, fSV= 125KHz)
Hsync and Vsync polarity
Hsync and Vsync presence needed for implementing the VESA DPMS standard
Integrated composite sync separation
Integrated signal generators for generating :
Free running horizontal and vertical sync pulses
Clamping pulse(Back porch, Front porch)
Pattern signal (white picture, black picture, cross hatch and inverse cross hatch)
Special option :
Missing sync pulse insertion
All measured parameters are stored in Special Function Register such that the data is available at any time.
The block diagram of the complete sync processor is given in Figure 19-1
19.1 Sync input signals
The sync inputs are able to handle standard TTL level sync sig-
nals. From Figure 19-1 it can be seen that both the HSYNCin and
SOGin inputs accept composite sync signals. The HSYNCin and
VSYNCin input is meant to be connected to the Hsync and Vsync
of the VGA cable while SOGin input is meant to be connected to
a sync slicer in order to handle Sync-On-Green at the video input.
This last signal should have a TTL level also. The selection be-
tween the HSYNCin and the SOGin inputs, as well as the selec-
tion between the VSYNCin and separated Vsync, can be done via
software.
Table 19-1 Sync Input selection
19.2 Horizontal polarity correction
In order to simplify the processing in the following stages, the
HSYNC polarity correction circuit is able to convert the input
sync signals to positive polarity signals in all situations. This cor-
rection is achieved by the aid of HPOL and HP.
HPOL and HP are only settled down in several horizontal scan-
ning lines or a few milliseconds after power-on or timing mode
change.
19.3 Vertical polarity correction
The purpose of the vertical polarity correction is similar to the
horizontal polarity correction. To get the correct resultafter pow-
er-on or a timing mode change, at least 5 frames is needed.
19.4 Vertical sync separation
This block separates the vertical sync from a composite sync sig-
nal. At approximately 1/4 of each HSYNC line the logical level
is latched. This yields a slightly delayed vertical sync signal.
Special precautions have been taken to suppress equalizing puls-
es when present and to allow both polarities of the composite sig-
nal.The format of the composite sync signal can be standard, as
given in Figure 19-2, or can be one of the non standard format as
given in Figure 19-3
Select Flag
HSEL
Signal to detector
0 : HSYNCin
1 : SOGin
VSEL
0 : VSYNCin
1 : Separated VSYNC
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