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| 型號(hào)： | HMS30C7210 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ARM Based 32-Bit Microprocessor |
| 中文描述： | 基于ARM的32位微處理器 |
| 文件頁(yè)數(shù)： | 131/161頁(yè) |
| 文件大小： | 973K |
| 代理商： | HMS30C7210 |
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HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
131
(ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows:
If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5.
If ARB_SEL bits are 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5.
If ARB_SEL bits are 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5.
If ARB_SEL bits are 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5.
Note that REQ0 of an arbiter is always the highest priority, and REQ5 is the lowest one. In addition,
by changing the ARB_SEL bits, we can rotate the priority of REQ1 - REQ4.
Here, if ARB_MODE bit is set to 0, ARB_SEL bits are not automatically changed, thus the arbiter
operates in the fixed priority mode. (Note that even in this mode, we can change the priority by
manually changing the ARB_SEL bits.). On the other hand, if ARB_MODE bit is 1, ARB_SEL bits
are changed in rotation fashion, e.g., if REQ1 is serviced, ARB_SEL bits are changed to 01b
automatically so as to make REQ1 the lowest priority one. The detailed rule of ARB_SEL change is
as follows.
If REQ0 or REQ5 is serviced, ARB_SEL bits are not changed at all.
If REQ1 is serviced, ARB_SEL bits are changed to 01b.
If REQ2 is serviced, ARB_SEL bits are changed to 10b.
If REQ3 is serviced, ARB_SEL bits are changed to 11b.
If REQ4 is serviced, ARB_SEL bits are changed to 00b.
2.12.1.
User Accessible Registers (Base = 0x1930_0000)
There are five control registers in the interrupt controller: source pending register, interrupt mode
register, mask register, priority register, and interrupt pending register.
All the interrupt requests from the interrupt sources are first registered in the source pending register.
They are divided into two groups based on the interrupt mode register, i.e., one NMI request and the
remaining IRQ requests. Arbitration process is performed for the multiple IRQ requests based on
the priority register.
2.12.1.1.
SOURCE PENDING REGISTER (SRCPND, offset = 0x00)
SRCPND register is composed of 32 bits each of which is related to an interrupt source. Each bit is
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