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參數(shù)資料
| 型號(hào)： | HMP8191 |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Encoder |
| 中文描述： | NTSC / PAL視頻編碼器 |
| 文件頁數(shù)： | 29/32頁 |
| 文件大?。?/td> | 227K |
| 代理商： | HMP8191 |
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29
Application Information
PCB Considerations
A PCB board with a minimum of 4 layers is recommended,
with layers 1 and 4 (top and bottom) for signals and internal
layers 2 and 3 for power and ground. The PCB layout should
implement the lowest possible noise on the power and
ground planes by providing excellent decoupling. PCB trace
lengths between groups of VAA and GND pins should be as
short as possible.
Component Placement
The optimum layout places the HMP8190/HMP8191 at the
edge of the PCB and as close as possible to the video output
connector. External components should be positioned as
close as possible to the appropriate pin, ideally such that
traces can be connected point to point. Chip capacitors are
recommended where possible, with radial lead ceramic
capacitors the second-best choice.
Traces containing digital signals should not be routed over,
under, or adjacent to the analog output traces to minimize
crosstalk. If this is not possible, coupling can be minimized
by routing the digital signals at a 90 degree angle to the
analog signals. The analog output traces should also not
cross over or under the V
CC
power plane to maximize high-
frequency power supply rejection.
Power and Ground Planes
A common ground plane for all devices, including the
HMP8190/HMP8191, is recommended. However, placing the
encoder on an electrically connected GND peninsula reduces
noise levels. All GND pins on the HMP8190/HMP8191 must
be connected to the ground plane. Typical power and ground
planes are shown in Figure 26.
The small connection between the ground areas should be
made wide enough so that most of the encoders digital inputs
can be routed over or under it. It is especially important that
the CLK and CLK2 signals cross through the connection.
The HMP8190/HMP8191 should have its own power plane
that is isolated from the common power plane of the board,
with a gap between the two power planes of at least 1/8 inch.
All V
AA
pins of the HMP8190/HMP8191 must be connected
to this isolated power plane.
The HMP8190/HMP8191 power plane should be connected
to the board’s normal V
CC
power plane at a single point
though a low-resistance ferrite bead, such as a Ferroxcube
5659065-3B, Fair-Rite 2743001111, or TDK BF45-4001. The
ferrite bead provides resistance to switching currents,
improving the performance of HMP8190/HMP8191. A single,
large capacitor should also be used between the
HMP8190/HMP8191 power plane and the ground plane to
control low-frequency power supply ripple.
For proper operation, power supply decoupling is required. It
should be done using a 0.1
μ
F ceramic capacitor in parallel
with a 0.01
μ
F chip capacitor for each group of V
AA
pins to
ground. These capacitors should be located as close to the
V
AA
and GND pins as possible, using short, wide traces.
If a separate linear regulator is used to provide power to the
HMP8190/HMP8191 power plane, the power-up sequence
should be designed to ensure latchup will not occur. A
separate linear regulator is recommended if the power
supply noise on the V
AA
pins exceeds 200mV. About 10% of
the noise (that is less than 1MHz) on the V
AA
pins will couple
onto the analog outputs.
FIGURE 24. H SYNC JITTER IN A FRAME (PAL)
FIGURE 25. SCH PHASE MEASUREMENT
Typical Performance Curves
(Continued)
HMP8190, HMP8191
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