參數(shù)資料
型號(hào)： HMP8156A
廠商： Intersil Corporation
英文描述： NTSC/PAL Encoders
中文描述： 的NTSC / PAL編碼器
文件頁(yè)數(shù)： 6/34頁(yè)
文件大?。?/td> 256K
代理商： HMP8156A
6
Normal 8-Bit YCbCr Format
When 8-bit YCbCr format is selected and 2X upscaling or
flicker filtering is not enabled, the data is latched on each
rising edge of CLK2. The pixel data must be [Cb Y Cr Y’ Cb Y
Cr Y’ . . . ], with the first active data each scan line being Cb
data. Overlay data is latched when the Y input data is latched.
The pixel and overlay input timing is shown in Figure 1.
As inputs, BLANK, HSYNC, and VSYNC are latched on
each rising edge of CLK2. As outputs, BLANK, HSYNC, and
VSYNC are output following the rising edge of CLK2. If the
CLK pin is configured as an input, it is ignored. If configured
as an output, it is one-half the CLK2 frequency.
8-Bit YCbCr Format with 2X Upscaling
When 8-bit YCbCr format is selected and 2X upscaling is
enabled, the data is latched on the rising edge of CLK2 while
CLK is low. The pixel data must be [Cb Y Cr Y’ Cb Y Cr
Y’. . . ], with the first active data each scan line being Cb
data. Overlay data is latched on the rising edge of CLK2 that
latches Y pixel input data. The pixel and overlay input timing
is shown in Figure 2.
As inputs, BLANK, HSYNC, and VSYNC are latched on the
rising edge of CLK2 while CLK is low. As outputs, HSYNC,
VSYNC, and BLANK are output following the rising edge of
CLK2 while CLK is high. In this mode of operation, CLK is
one-half the CLK2 frequency.
TABLE 5. PIXEL INPUT AND CONTROL SIGNAL I/O TIMING
INPUT FORMAT
M
(
INPUT PORT SAMPLING
VIDEO TIMING CONTROL
(NOTE 2)
CLK FREQUENCY
PIXEL DATA
OVERLAY DATA
INPUT SAMPLE
OUTPUT ON
INPUT
OUTPUT
8-Bit YCbCr
Norm
Every rising edge
of CLK2
Same edge that
latches Y
Every rising edge
of CLK2
Any rising edge of
CLK2
Ignored
One-half
CLK2
2X
Rising edge of
CLK2 when CLK is
low.
Same edge that
latches Y data
Rising edge of
CLK2 when CLK is
low.
Rising edge of
CLK2 when CLK is
high.
One-half CLK2
FF
Not Available
16-Bit YCbCr,
16-Bit RGB,
or
24-Bit RGB
Norm
Rising edge of CLK2 when CLK is low
Rising edge of
CLK2 when CLK is
high.
One-half CLK2
2X
2nd rising edge of CLK2 when CLK is low
Either rising CLK2
edge when CLK is
high
One-fourth CLK2
FF
Every rising edge
of CLK2
Same edge that
latches Y
Every rising edge
of CLK2
Any rising edge of
CLK2
Ignored
One-half
CLK2
BT.656
Norm
Every rising edge
of CLK2
Same edge that
latches Y
Not Allowed
Any rising edge of
CLK2
Ignored
One-half
CLK2
2X
Not Available
FF
Not Available
NOTES:
1. Encoderoperatingmodes:
Norm = Full size input, Flicker filter disabled.
2X = SIF size input, Flicker filter disabled.
FF = Full size input, Flicker filter enabled.
(2X upscaling and flicker filtering are mutually exclusive.)
2. VideotimingcontrolsignalsincludeHSYNC,VSYNC,BLANKandFIELD.ThesyncandblankingI/Odirectionsareindependent;FIELDisalways
an output.
HMP8154, HMP8156A
相關(guān)PDF資料
PDF描述
HMP8154EVAL1 NTSC/PAL Encoders
HMP8190 NTSC/PAL Video Encoder
HMP8190CN NTSC/PAL Video Encoder
HMP8190EVAL1 NTSC/PAL Video Encoder
HMP8191 NTSC/PAL Video Encoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HMP8156ACN 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 64MQFP,0+70C NTSC/PAL VIDEO ENCODER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
HMP8156ACNZ 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 W/ANNEAL 64MQFP 0+70 ENCODER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray
HMP8156CN 制造商:Rochester Electronics LLC 功能描述:- Bulk
HMP8156EVAL1 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:NTSC/PAL Encoders
HMP8156EVAL2 制造商:Rochester Electronics LLC 功能描述:- Bulk
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