- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385388 > HMP8156A (Intersil Corporation) NTSC/PAL Encoders PDF資料下載
參數(shù)資料
| 型號： | HMP8156A |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Encoders |
| 中文描述： | 的NTSC / PAL編碼器 |
| 文件頁數(shù)： | 17/34頁 |
| 文件大?。?/td> | 256K |
| 代理商： | HMP8156A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
17
Host Interfaces
Reset
The HMP8154/HMP8156A resets to its default operating
mode on power up, when the reset pin is asserted for at
least four CLK cycles, or when the software reset bit of the
host control register is set. During the reset cycle, the
encoder returns its internal registers to their reset state and
deactivates the I
2
C interface.
I
2
C Interface
The HMP8154/HMP8156A provides a standard I
2
C interface
and supports fast-mode (up to 400 Kbps) transfers. The
device acts as a slave for receiving and transmitting data
only. It will not respond to general calls or initiate a transfer.
The encoder’s slave address is either 0100 000x
B
when the
SA input pin is low or 0100 001x
B
when it is high. (The ‘x’ bit
in the address is the I
2
C read flag.)
The I
2
C interface consists of the SDA and SCL pins. When
the interface is not active, SCL and SDA must be pulled high
using external 4-6k
pull-up resistors. The I
2
C clock and
data timing is shown in Figures 20 and 21.
During I
2
C write cycles, the first data byte after the slave
address specifies the sub address, and is written into the
address register. Only the seven LSBs of the subaddress are
used; the MSB is ignored. Any remaining data bytes in the
I
2
C write cycle are written to the control registers, beginning
with the register specified by the address register. The 7-bit
address register is incremented after each data byte in the
I
2
C write cycle. Data written to reserved bits within registers
or reserved registers is ignored.
During I
2
C read cycles, data from the control register
specified by the address register is output. The address
register is incremented after each data byte in the I
2
C read
cycle. Reserved bits within registers return a value of “0”.
Reserved registers return a value of 00
H
.
The HMP8154/HMP8156A’s operating modes are
determined by the contents of its internal registers which are
accessed via the I
2
C interface. All internal registers may be
written or read by the host processor at any time. However,
some of the bits and words are read only or reserved and
data written to these bits is ignored.
Table 10 lists the HMP8154/HMP8156A’s internal registers.
Their bit descriptions are listed in Tables 11-30.
TABLE 10. CONTROL REGISTER NAMES
SUB ADDRESS
(HEX)
CONTROL REGISTER
RESET
CONDITION
00
01
02
03
04
05
06
07-0E
0F
10
11
12
13
14-1F
20
21
22
23
24
25
26
27
28-2F
30-7F
Product ID
Output Format
Input Format
Video Processing
Timing I/O 1
Timing I/O 2
Aux Data Enable
Reserved
Host Control
Closed Caption_21A
Closed Caption_21B
Closed Caption_284A
Closed Caption_284B
Reserved
Start H_Blank Low
Start H_Blank High
End H_Blank
Start V_Blank Low
Start V_Blank High
End V_Blank
Field Control 1
Field Control 2
Reserved
Test and Unused
54
H
00
H
06
H
A0
H
00
H
00
H
00
H
-
0C
H
80
H
80
H
80
H
80
H
-
4A
H
03
H
7A
H
03
H
01
H
13
H
80H
00H
-
-
FIGURE 20. I
2
C SERIAL TIMING FLOW
FIGURE 21. REGISTER WRITE PROGRAMMING FLOW
SDA
SCL
START
CONDITION
S
1-7
ADDRESS
8
R/W
9
ACK
1-7
DATA
8
9
ACK
STOP
CONDITION
P
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
FROM MASTER
FROM ENCODER
0x40 OR
0x42
DATA WRITE
DATA
DATA
DATA READ
REGISTER
POINTED
TO BY
SUBADDR
REGISTER
POINTED
TO BY
SUBADDR
0x41 OR
0x43
P
NA
A
S
CHIP ADDR
A
SUB ADDR
A
DATA
DATA
A
A
P
A
CHIP ADDR
S
A
SUB ADDR
A
CHIP ADDR
S
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
0x40 OR
0x42
HMP8154, HMP8156A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMP8154EVAL1 | NTSC/PAL Encoders |
| HMP8190 | NTSC/PAL Video Encoder |
| HMP8190CN | NTSC/PAL Video Encoder |
| HMP8190EVAL1 | NTSC/PAL Video Encoder |
| HMP8191 | NTSC/PAL Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMP8156ACN | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 64MQFP,0+70C NTSC/PAL VIDEO ENCODER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8156ACNZ | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 W/ANNEAL 64MQFP 0+70 ENCODER RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時(shí)間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8156CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8156EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8156EVAL2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。