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參數(shù)資料
| 型號(hào)： | HMP8117CNZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PDSO80 |
| 封裝： | PLASTIC, MS-022GB-1, MQFP-80 |
| 文件頁(yè)數(shù)： | 22/45頁(yè) |
| 文件大?。?/td> | 552K |
| 代理商： | HMP8117CNZ |
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22
FN4643.3
April 19, 2007
Control Registers
R
TABLE 10. CONTROL REGISTER SUMMARY
SUB-
ADDRESS
CONTROL REGISTER
RESET/
DEFAULT
VALUE
USE
VALUE
COMMENTS
00
H
01
H
02
H
03
H
04
H
05
H
06
H
08
H
0A
H
0B
H
0C
H
0E
H
0F
H
10
H
11
H
12
H
14
H
/13
H
15
H
16
H
17
H
18
H
19
H
1A
H
1B
H
1C
H
1D
H
1E
H
1F
H
20
H
-23
H
24
H
-29
H
31
H
/30
H
32
H
34
H
/33
H
35
H
36
H
37
H
41
H
42
H
50
H
51
H
52
H
53
H
7F
H
Sub-Addresses: 40
H
, 43
H
-4F
H
are reserved. Reads from these registers may return non-zero values.
Sub-Addresses: 07
H
, 09
H
, 0D
H
, 2A
H
-2F
H
, 38
H
-3F
H
and 54
H
-7E
H
are unused. Reads from these registers return 00
H
. Writes are ignored.
Product ID
16
H
or 17
H
19
H
00
H
00
H
09
H
10
H
52
H
04
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
7A
H
03
H
/4A
H
FE
H
1F
H
00
H
00
H
80
H
00
H
80
H
40
H
80
H
10
H
00
H
80
H
00
H
03
H
/4A
H
7A
H
01
H
/02
H
12
H
30
H
20
H
26
H
00
H
0C
H
14
H
02
H
00
H
01
H
Returns last two digits of part number in hex format.
Input Format
Defaults to auto-detect of input video standard.
Output Format
Defaults to 16-bit YCbCr data format.
Output Control
C0
H
Set Bits 7-6 to enable data and timing outputs.
Genlock Control
Defaults to 27MHz CLK2, Rectangular Pixel Mode
Analog Input Control
Defaults to input signal select = CVBS1.
Color Processing
Luma Processing
Sliced VBI Data Enable
Sliced VBI Data Output
VBI Data Status
Video Status
Interrupt Mask
Interrupt Status
Raw VBI Control
Raw VBI Start Count
Raw VBI Stop Count MSB/LSB
Raw VBI Line Mask_7_0
Raw VBI Line Mask_15_8
Raw VBI Line Mask_18_16
Brightness
Contrast
Hue
Saturation
Color Gain Adjust
Video Gain Adjust
Sharpness
Host Control
Set bit 7 for Soft Reset. Set bit 6 for Power Down.
Closed Caption Data Registers
WSS Data & CRC Registers
Start H_BLANK MSB/LSB
Table 3
BLANK programming changes for each video standard.
End H_BLANK
Table 3
(same as above)
Start V_BLANK MSB/LSB
Table 3
(same as above)
End V_BLANK
Table 3
(same as above)
End HSYNC
Table 3
(same as above)
HSYNC Detect Window
90
H
A wider window tolerates poorly timed video sources.
MV Control
Reserved
30
H
21
H
Set bits 5-4 to 11
B
for optimum performance.
A slower PFG improves AGC stability.
Programmable Fractional Gain
MV Stripe Gate
Reserved
22
H
F0
H
Set bit 5 to “1” for optimum performance.
AGC Hysteresis
Larger hysteresis improves AGC stability.
Device Revision
Production baseline revision is 01
H
.
HMP8117
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