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參數(shù)資料
| 型號： | HMP8117CNZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PDSO80 |
| 封裝： | PLASTIC, MS-022GB-1, MQFP-80 |
| 文件頁數(shù)： | 21/45頁 |
| 文件大小： | 552K |
| 代理商： | HMP8117CNZ |
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21
FN4643.3
April 19, 2007
In order to perform a read from a specific control register
within the HMP8117, an I
2
C bus write must first be
performed to properly setup the address register. Then an
I
2
C bus read can be performed to read from the desired
control register(s). As a result of needing the write cycle for a
read cycle there are actually two START conditions as
shown in Figure 19. The address register is then
auto-incremented after each byte read during the I
2
C read
cycle. Reserved registers return a value of
00
H
.
FIGURE 17. I
2
C TIMING DIAGRAM
SDA
SCL
t
BUF
t
LOW
t
HIGH
t
R
t
F
t
SU:DATA
t
HD:DATA
tSU:STOP
SDA
SCL
START
CONDITION
S
1-7
ADDRESS
8
R/W
9
ACK
1-7
DATA
8
9
ACK
STOP
CONDITION
P
FIGURE 18. I
2
C SERIAL DATA FLOW
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
FROM MASTER
FROM HMP8117
0x88
DATA WRITE
DATA
DATA
0x88
DATA READ
0x89
1000 1000 (R/W)
1000 1000
FIGURE 19. REGISTER WRITE/READ FLOW
S
CHIP ADDR
A
SUB ADDR
DATA
DATA
P
NA
CHIP ADDR
S
SUB ADDR
CHIP ADDR
S
P
A
A
A
A
A
A
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
A
REGISTER
POINTED
TO BY
SUB ADDR
OPTIONAL FRAME
MAY BE REPEATED
n TIMES
HMP8117
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HMP8154 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8154EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8156 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoder |
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