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參數(shù)資料
| 型號： | HMP8117CNZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PDSO80 |
| 封裝： | PLASTIC, MS-022GB-1, MQFP-80 |
| 文件頁數(shù)： | 14/45頁 |
| 文件大?。?/td> | 552K |
| 代理商： | HMP8117CNZ |
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14
FN4643.3
April 19, 2007
8-Bit BT.656 Output
For the BT.656 output mode, data is output following each
rising edge of CLK2. The BT.656 EAV and SAV formats are
shown in Table 5 and the pixel output timing is shown in
Figure 14. The EAV and SAV timing is determined by the
programmed horizontal and vertical blank timing.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2.
During the blanking intervals, the YCbCr outputs have a
value of 16 for Y and 128 for Cb and Cr, unless ancillary data
is present.
NOTES:
12. Y
0
is the first active luminance pixel of a line. Cb
0
and Cr
0
are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due
to the 4:2:2 subsampling.
13. BLANK is asserted per Figure 7.
14. DVALID is asserted for every valid pixel during both active and blanking regions.
FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
Y
0
Cb
0
Y
1
Cr
0
Y
2
Cb
2
Y
3
Cr
2
Y
4
Cb
4
CLK
DVALID
P15-P8
P7-P0
t
DVLD
NOTES:
15. BLANK is asserted per Figure 7.
16. DAVLID is asserted for every valid pixel during both active and blanking regions. DVALID is not a 50% duty cycle synchronous output and will
appear to jitter as the Output Sample Rate converter adjusts the output timing for various data rates and clock frequency inputs.
FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 1)
R0
G
0
R
1
G
0
R
2
G
2
R
3
G
2
R
4
G
4
CLK
DVALID
BLANK
t
DVLD
B
0
B
1
B
2
B
3
B
4
P15-P11
[P14-P10]
P10-P5
[P9-P5]
P4-P0
HMP8117
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