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參數(shù)資料
| 型號(hào)： | HM6P5331 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | HM6P5331 - 2.0GHz/500MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PBGA24 |
| 封裝： | PLASTIC, LGA-24 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 195K |
| 代理商： | HM6P5331 |
PRELIMINARY
Phase Detector Polarity
Depending upon VCO characteristics, R16 bit should be
set accordingly:
When VCO characteristics are positive like (1), R16
should be set HIGH; When VCO characteristics are
negative like (2), R16 should be set LOW.
Serial Data Input Timing
&'&
()*
(+
(+
)
,-.
,(-.
,-.
,(-.
NOTES:
1. Parenthesis data indicates programmable reference divider data.
2. Data shifted into register on clock rising edge.
3. Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around V
DD
/2. The test waveform
has an edge rate of 0.6V/ns with amplitudes of 2.2V at V
DD
= 2.7V and 2.6V at V
DD
= 3.6V.
Phase Comparator and Internal Charge Pump Characteristics
"
(
"
" /"
" 0"
" 1"
" 1"
" 1"
NOTES:
1. Phase difference detection range: -2
2. The minimum width pump up and pump down current pulse occur at the D
O
pin when the loop is locked.
3. R16 = HIGH
to +2
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