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參數(shù)資料
| 型號： | HM6P5331 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | HM6P5331 - 2.0GHz/500MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PBGA24 |
| 封裝： | PLASTIC, LGA-24 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 195K |
| 代理商： | HM6P5331 |
PRELIMINARY
Programmable Divide (N Counter)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the
Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-
bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter),
MSB first. Serial data format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter
does not have don’t care bits.
7-Bit Swallow Counter Divide Ratio (A Counter)
RF
N
5
0
0
DIVIDE
RATIO A
0
1
N
7
0
0
N
6
0
0
N
4
0
0
N
3
0
0
N
2
0
0
N
1
0
1
1
1
1
1
1
1
1
127
NOTES:
1. Divide ratio 0 to 127
2. B
A
IF
N
5
X
X
DIVIDE
RATIO A
0
1
N
7
X
X
N
6
X
X
N
4
0
0
N
3
0
0
N
2
0
0
N
1
0
1
X
X
X
1
1
1
1
15
X = Don’t care condition
11-Bit Programmable Counter Divide Ratio (B Counter)
DIVIDE
RATIO A
3
4
N
18
0
0
N
17
0
0
N
16
0
0
N
15
0
0
N
14
0
0
N
13
0
0
N
12
0
0
N
11
0
0
N
10
0
1
N
9
1
0
N
8
1
0
1
1
1
1
1
1
1
1
1
1
1
2047
NOTES:
1. Divide ratio 3 to 2047 (divide ratios less than 3 are prohibited).
2. B
A
Pulse Swallow Function
f
VCO
= [(P
f
VCO
: Output frequency of external voltage controlled oscillator (VCO)
B:
Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A:
Preset divide ratio of binary 7-bit swallow counter (0
f
OSC
: Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P:
Preset modulus of dual modulus prescaler (for IF: P=8 or 16; for RF: P=64 or 128)
B) + A]
f
OSC
/R
A
127 {RF}, 0
A
15 {IF}, A
B)
!"#$!%
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