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參數(shù)資料
| 型號(hào)： | HM6P5331 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | XO, clock |
| 英文描述： | HM6P5331 - 2.0GHz/500MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PBGA24 |
| 封裝： | PLASTIC, LGA-24 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 195K |
| 代理商： | HM6P5331 |
PRELIMINARY
Absolute Maximum Ratings
Power Supply Voltage
VDD -0.3V to +4.2V
VPP -0.3V to +4.2V
Voltage on Any Pin
with GND = 0V (V
I
) -0.3V to +4.2V
Storage Temperature Range (T
S
) -65
°
C to +150
°
C
Lead Temperature (solder 4 sec.) (T
L
) 260
°
C
Thermal Resistance(Typical)
θ
JA
(
°
C/W)
TSSOP Package 130
°
C
Operating Conditions
Power Supply Voltage
VDD 2.7V to 3.6V
VPP VDD to 3.6V
Operating Temperature(T
A
) -40
°
C to 85
°
C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Other conditions
above those indicated in the operational sections of this specification are not implied.
Electrical Characteristics
V
DD
= 3.0V, -40
°
C < T
A
< 85
°
C, Except as Specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RF
V
DD
=2.7V to 3.6V,
f
Φ
= 10KHz
V
DD
=2.7V to 3.6V,
f
Φ
= 10KHz
V
DD
=3.0V
3.2
mA
I
DD
Power Supply Current
IF
1.2
5.4
mA
I
DD-PWDN
f
IN
RF
f
IN
IF
f
OSC
f
Φ
Pf
IN
RF
Pf
IN
IF
V
OSC
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
V
OH
V
OL
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
Powerdown Current
Operating Frequency
1
-
10
2.0
μ
A
GHz
0.5
Operating Frequency
50
-
500
MHz
Oscillator Frequency.
4
-
40
MHz
Maximum Phase Detector Freq.
10
-
-
MHz
RF Input Sensitivity
V
DD
=2.7V to 3.6V
V
DD
=2.7V to 3.6V
OSC
IN
*
- 8.5
-
0
dBm
IF Input Sensitivity
-10
-
0
dBm
Oscillator Sensitivity
0.5
-
-
V
PP
V
High Level Input Voltage
0.8 V
DD
-
-
-
Low Level Input Voltage
*
-
0.2 V
DD
1.0
V
μ
A
μ
A
μ
A
μ
A
V
V
ns
High Level Input Current
V
IH
=V
DD
=3.6V*
V
IL
=0V, V
DD
=3.6V*
V
IH
=V
DD
=3.6V
V
IL
=0V, V
DD
=3.6V
I
OH
= -500
μ
A
I
OL
= 500
μ
A
See Data Input Timing
-1.0
-
Low Level Input Current
-1.0
-
1.0
Oscillator Input Current
-
-
100
Oscillator Input Current
-100
-
-
High-Level Output Voltage
V
DD
-0.4
-
-
-
Low-Level Output Voltage
-
0.4
Data Clock Setup Time
50
-
-
Data Clock Hold Time
See Data Input Timing
10
-
Clock Pulse Width High
See Data Input Timing
50
-
-
Clock Pulse Width Low
See Data Input Timing
50
-
-
Clock to Load Enable Setup Time
See Data Input Timing
50
-
-
Load Enable Pulse Width
See Data Input Timing
50
-
-
* Clock, Data and LE. Does not include f
IN
RF, f
IN
IF and OSC
IN
.
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