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參數(shù)資料
| 型號： | HM658512AI |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M PSRAM (512-kword ×8-bit)(4 M PSRAM (512k字 ×8位)) |
| 中文描述： | 4個M移動存儲芯片（512 KWord的× 8位）（4個M移動存儲芯片（為512k字× 8位）） |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 129K |
| 代理商： | HM658512AI |
HM658512AI Series
8
HM658512AI
-8
-10
-12
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Notes
Refresh command delay time
t
RFD
t
FP
t
FAP
40
—
50
—
60
—
ns
Refresh precharge time
40
—
40
—
40
—
ns
Refresh command pulse width for
automatic refresh
80 n
8
μ
80 n
8
μ
80 n
8
μ
s
Automatic refresh cycle time
t
FC
t
FAS
130
—
160
—
190
—
ns
Refresh command pulse width for
self refresh
8
—
8
—
8
—
μ
s
Refresh reset time from self refresh t
RFS
Refresh period
600
—
600
—
600
—
ns
9
t
REF
—
32
—
32
—
32
ms
2048
cycle
Notes: 1. t
CHZ
, t
OHZ
, t
WHZ
are defined as the time at which the output achieves the open circuit condition.
2. t
CHZ
, t
CLZ
, t
OHZ
, t
OLZ
, t
WHZ
and t
OW
are sampled under the condition of t
T
= 5 ns and not 100% tested.
3. A write occurs during the overlap of low
CE
and low
WE
. Write end is defined at the earlier of
WE
going high or
CE
going high.
4. If the
CE
low transition occurs simultaneously with or from the
WE
low transition, the output
buffers remain in high impedance state.
5. In write cycle,
OE
or
WE
must disable output buffers prior to applying data to the device and at
the end of write cycle data inputs must be floated prior to
OE
or
WE
turning on output buffers.
During this period, I/O pins are in the output state, therefore the input signals of opposite phase
to the outputs must not be applied.
6. Transition time t
is measured between V
(min) and V
IL
(max). V
IH
(min) and V
IL
(max) are
reference levels for measuring timing of input signals.
7. After power-up, pause for more than 100
μ
s and execute at least 8 initialization cycles.
8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed
within 15
μ
s after self refresh, in order to meet the refresh specification of 32 ms and 2048
cycles.
9. At the end of self refresh, refresh reset time (t
) is required to reset the internal self refresh
operation of the RAM. During t
,
CE
and
OE
/
RFSH
must be kept high. If automatic refresh
follows self refresh, low transition of
OE
/
RFSH
at the beginning of automatic refresh must not
occur during t
RFS
period.
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| HM658512ALFP-10 | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
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| HM658512ALRR-10 | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM658512ALFP-10 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALFP-10V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALFP-7 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALFP-7V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALFP-8 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
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