參數(shù)資料
型號(hào): HM62W8512BI
廠商: Hitachi,Ltd.
英文描述: 4 M SRAM (512-kword×8-bit)(4 M 靜態(tài)RAM(512k字×8位))
中文描述: 四米的SRAM(512 - KWord的× 8位)(4個(gè)M靜態(tài)隨機(jī)存儲(chǔ)器(為512k字× 8位))
文件頁數(shù): 7/12頁
文件大小: 59K
代理商: HM62W8512BI
HM62W8512BI Series
7
3.A write occurs during the overlap (t
WP
) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going
high or WE going high. t
WP
is measured from the beginning of write to the end of write.
4.t
CW
is measured from CS going low to the end of write.
5.t
AS
is measured from the address valid to the beginning of write.
6.t
WR
is measured from the earlier of WE or CS going high to the end of write cycle.
7.During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8.If the CS low transition occurs simultaneously with the WE low transition or after the WE
transition, the output remain in a high impedance state.
9.Dout is the same phase of the write data of this write cycle.
10.Dout is the read data of next address.
11.If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12.In the write cycle with OE low fixed, t
WP
must satisfy the following equation to avoid a
problem of data bus contention. t
WP
t
DW
min + t
WHZ
max
Timing Waveforms
Read Timing Waveform (WE = V
IH
)
t
AA
t
CO
t
RC
t
LZ
t
OE
t
OLZ
t
HZ
t
OHZ
Valid Data
Address
CS
OE
Dout
t
OH
相關(guān)PDF資料
PDF描述
HM62W8512BLTT-7UL Octal Buffer/Driver With Open-Collector Outputs 20-PDIP -40 to 85
HM62W8512BLFP-5 4 M SRAM (512-kword x 8-bit)
HM62W8512BLFP-5SL 4 M SRAM (512-kword x 8-bit)
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HM62W8512BLFP-7 4 M SRAM (512-kword x 8-bit)
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