參數(shù)資料
型號(hào)： HM5113165F
廠商： Hitachi,Ltd.
英文描述： 128M EDO DRAM(128M 擴(kuò)展數(shù)據(jù)輸出模式動(dòng)態(tài)RAM)
中文描述： 128M的內(nèi)存江戶（128M的擴(kuò)展數(shù)據(jù)輸出模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 461K
代理商： HM5113165F
HM5113165F Series
14
20.t
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode
RAS
cycle (EDO page
mode mix cycle (1), (2)), minimum value of
CAS
cycle (t
+ t
+ 2 t
) becomes greater than the
specified t
(min) value. The value of
CAS
cycle time of mixed EDO page mode is shown in EDO
page mode mix cycle (1) and (2).
21.Data output turns off and becomes high impedance from later rising edge of
RAS
and
CAS
. Hold
time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS
between t
OHR
and t
OH
and between t
OFR
and t
OFF
.
22.t
defines the time at which the output level go cross. V
OL
= 0.8 V, V
OH
= 2.0 V of output timing
reference level.
23.Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms
period on the condition a and b below.
a. Enter self refresh mode within 15.6
μ
s after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6
μ
s after exiting from self refresh mode.
24.In case of entering from
RAS
-only-refresh, it is necessary to execute CBR refresh before and after
self refresh mode according as note 23.
25 At t
> 100
μ
s, self refresh mode is activated, and not activated at t
< 10
μ
s. It is undefined
within the range of 10
μ
s
≤
t
RASS
≤
100
μ
s. For t
RASS
≥
10
μ
s, it is necessary to satisfy t
RPS
.
26.t
, t
, t
, t
WCS
, t
WCH
, t
, t
, t
, t
CHR
, t
RCH
, t
CPA
, t
CPW
, t
CWL
, t
DH
, t
DS
, t
CHS
and t
CP
are determined by
each of
UCAS
/
independently.
27.XXX: H or L (H: V
IH
(min)
≤
V
IN
≤
V
IH
(max), L: V
IL
(min)
≤
V
IN
≤
V
IL
(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied V
IH
or V
IL
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5113165FLTD-6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M EDO DRAM (8-Mword × 16-bit) 4k refresh
HM5113165FTD-6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M EDO DRAM (8-Mword × 16-bit) 4k refresh
HM5113165LTD-6 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M EDO DRAM (8-Mword × 16-bit) 4k refresh
HM5113805F-6 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
HM5113805FLTD-6 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
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