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參數(shù)資料
| 型號： | HM5112805FTD-6 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh |
| 中文描述： | 128M的內(nèi)存江戶（16 Mword × 8位）8K的refresh/4k刷新 |
| 文件頁數(shù)： | 15/34頁 |
| 文件大小： | 480K |
| 代理商： | HM5112805FTD-6 |
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HM5112805F-6, HM5113805F-6
15
Self Refresh Mode
(L-version)
HM5112805FL/HM5113805FL
-6
Parameter
RAS
pulse width (self refresh)
RAS
precharge time (self refresh)
CAS
hold time (self refresh)
Notes: 1. AC measurements assume t
T
= 2 ns.
2. An initial pause of 200
μ
s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS
-only refresh or
CAS
-before-
RAS
refresh).
3. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RCD
(max) limit, than the access time is
controlled exclusively by t
CAC
.
4. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
5. Either t
OED
or t
CDD
must be satisfied.
6. Either t
DZO
or t
DZC
must be satisfied.
7. V
(min) and V
(max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V
IH
(min) and V
IL
(max).
8. Assumes that t
≤
t
(max) and t
≤
t
RAD
(max). If t
or t
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that t
RCD
≥
t
RCD
(max) and t
RCD
+ t
CAC
(max)
≥
t
RAD
+ t
AA
(max).
11.Assumes that t
RAD
≥
t
RAD
(max) and t
RCD
+ t
CAC
(max)
≤
t
RAD
+ t
AA
(max).
12.Either t
RCH
or t
RRH
must be satisfied for a read cycles.
13.t
(max), t
(max), t
(max) and t
(max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14.t
, t
, t
, t
and t
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if t
≥
t
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
≥
t
RWD
(min), t
CWD
≥
t
CWD
(min), and t
AWD
≥
t
AWD
(min), or t
CWD
≥
t
CWD
(min), t
AWD
≥
t
AWD
(min) and t
CPW
≥
t
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15.t
and t
are referred to
CAS
leading edge in early write cycles and to
WE
leading edge in
delayed write or read-modify-write cycles.
16.t
RASP
defines
RAS
pulse width in EDO page mode cycles.
17.Access time is determined by the longest among t
AA
, t
CAC
and t
CPA
.
18.In delayed write or read-modify-write cycles,
OE
must disable output buffer prior to applying data
to the device.
19.When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC
/V
SS
line noise, which causes to degrade V
IH
min/V
IL
max level.
Symbol
Min
Max
Unit
Notes
t
RASS
t
RPS
t
CHS
100
—
μ
s
25
110
—
ns
25
–50
—
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5113805F-6 | 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh |
| HM5113805FLTD-6 | 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh |
| HM5113805FTD-6 | 128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh |
| HM5112805F | 128M EDO DRAM(128M 擴展數(shù)據(jù)輸出模式動態(tài)RAM) |
| HM5113805F | 128 M EDO（Extended Data Output） DRAM(128M 擴展數(shù)據(jù)輸出模式動態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5112805LTD-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| HM5112805TD-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| HM5112805TD-5/HM5113805TD-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128M EDO DRAM (16-Mword X 8-Bit) 8K Refresh/4K Refre |
| HM5112805TD-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| HM5113165FLTD-6 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M EDO DRAM (8-Mword × 16-bit) 4k refresh |
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