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參數(shù)資料
| 型號(hào)： | HIP7030A2P |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PDIP28 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 44K |
| 代理商： | HIP7030A2P |
9-48
HIP7030A0
PD0-PD4 (Port D - Input/Output)
These five I/O lines comprise Port D. As with PA0-PA7, the
mode (i.e. - input or output) of each pin is software program-
mable. In addition a Special Function Register (SFRD)
allows configuring PD0 and PD1 as “strobed” outputs, and/or
PD2,PD3, and PD4 as inputs to an on-chip analog compara-
tor.
All Port D I/O lines are configured as inputs during power-on
or RESET.
VPWOUT (Variable Pulse Width Out - Output),
VPWIN (Variable Pulse Width In - Input)
These two lines are used to interface to the J1850 bus trans-
ceiver.
VPWOUT is the pulse width modulated output of the SEN-
DEC encoder block.
VPWIN is the inverted input to the SENDEC decoder block.
MISO (Master-in/Slave-out - Input/Output),
MOSI (Master-out/Slave-in - Input/Output),
SCK (Serial Clock - Input/Output),
SS (Slave Select - Input)
These four lines constitute the Serial Peripheral Interface
(SPI) communications port. The MCU can be configured as
a SPI “master” or as a SPI “slave”. In master mode MOSI
and SCK function as outputs and MISO functions as an
input. In slave mode MOSI and SCK are inputs and MISO is
an output. SS is always an input.
Serial data words are transmitted and received over the
MISO/MOSI lines synchronously with the SCK clock stream.
The word size is fixed at 8 bits. Single buffering is used
which results in an inherent inter-byte delay. The master
device always provides the synchronizing clock.
A low on the SS line causes the MCU to immediately
assume the role of slave, regardless of it’s current mode.
This allows multi-master systems to be constructed with
appropriate arbitration protocols.
ALC (Address Latch Control - Input)
The ALC input controls the timing and function of the
address and memory control lines (CE, RD, WE, and FS).
For more information on each of these lines refer to the
appropriate section.
When ALC is low the address and control lines are produced
coincident with data bus transitions of the HIP7030A0’s
machine cycle. This mode allows direct interfacing to indus-
try standard memory devices. Refer to the timing diagrams
in
Electrical Specifications
for more details.
Driving ALC high causes several changes in the behavior of
the address and control lines. These changes are intended
to facilitate design of development systems for the
HIP7030A2. When ALC is high the following occur:
The Internal RAM is disabled and accesses to RAM space
are mapped off-chip.
A0-A12, FS, and RD are produced t
CYC
cycle (i.e. 100ns
with a 10MHz clock) ahead of data bus transitions of the
HIP7030A0’s machine cycle. The earlier availability of
these address and control lines facilitates implementation
of break detection and bus tracing logic. External latching
of the address and control signals is required for interfac-
ing to the memory of the development tool. The timing of
CE and WE are not affected by ALC, and remain synchro-
nized with data bus transfers.
The RD signal is no longer gated with CE and is a full
cycle wide, when ALC is high. RD indicates whether the
ensuing data bus cycle will be a
read of
or
write to
mem-
ory-I/O space. It can be viewed as a R/W signal. RD pro-
vides R/W information for all cycles, internal as well as
external.
Resetting the HIP7030A0 with ALC = 1 disables the Slow
Clock Detect circuits. The Watchdog can be disabled by
writing to the Watchdog Status Register (WSR - location
$1E), which has special features when ALC is high. The
Slow Clock circuit is permanently disabled when ALC = 1.
If the Slow Clock detect circuitry were allowed to run, stop-
ping the CPU clock during breakpoint servicing would not
be possible. The watchdog should be reset by the tool
while interrogating the CPU.
The ALC input has an integrated pull-down device which
allows floating this pin when interfacing to industry standard
memory devices.
A0-A12
Address lines 0 through 12. When ALC = 0, A0-A12 are
coincident with data bus transfers. When ALC = 1, A0-A12
change t
CYC
ahead of the data bus transfers and must be
externally latched. See the timing diagrams in the
Electrical
Specifications
section for more details.
DB0-DB7
Bidirectional 8-bit non-multiplexed data bus lines. The data
bus is an input during all reads from external memory-I/O
space and during the first t
CYC
of every machine cycle. At all
other times it is an output. See the timing diagrams in the
Electrical Specifications
section for more details.
CE (Chip Enable - Output)
Chip Enable is an output signal used for selecting external
memory or I/O. A low level indicates when external memory
or I/O is being accessed. Note that the CE signal will not go
true when addressing the unused locations of Page 0 I/O
space even though the address lines will be valid.
RD (Read - Output)
RD is a status output signal which indicates direction of data
flow with respect to external or internal memory space (a low
level indicates a read from memory space). A read from
internal memory or I/O will place data on the external data
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