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參數(shù)資料
| 型號： | HIP7030A2P |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FPGA - 200000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PDIP28 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 44K |
| 代理商： | HIP7030A2P |
9-44
Specifications HIP7030A0
(1)
t
CYC
Read Cycle Time
200
-
ns
(2)
t
RDOSC
RD, FS Setup Time Before OSCB
0.5t
CYC
-25
-
ns
(3)
t
DVCEL
Access Time From CE
-
t
CYC
-80
ns
(4)
t
DVOSC
Access Time From OSCB
-
t
CYC
-70
ns
(5)
t
OSCAV
Address Setup Time Before OSCB
0.5t
CYC
-25
-
ns
(6)
t
OSCAX
Address Hold Time After OSCB
0.5t
CYC
-
ns
(7)
t
OSCAX
Data Hold Time After OSCB
10
-
ns
(8)
t
RDLDX
Data Bus Driven From CE
(Time to Data Active from High Impedance
State)
0
-
ns
(9)
t
OSCRD
RD, FS Hold Time After OSCB
0.5t
CYC
-
ns
(10)
t
OSCDS
OSCB to DS Propagation Delay
5
25
ns
NOTE:
1. Minimum frequency applies when ALC is high.
Write Cycle Timing (ALC = 1)
(See Figure 4) V
DD
= 5V
DC
±
10%, V
SS
= 0V
DC
, T
A
= -40
o
C to +125
o
C Unless Otherwise Specified.
NUMBER
SYMBOL
PARAMETER
MIN
MAX
UNITS
f
OSC
OSCB Operating Frequency
10
MHz
(1)
t
CYC
Write Cycle Time
200
-
ns
(2)
t
RDOSC
RD, FS Setup Time Before OSCB
0.5t
CYC
-25
-
ns
(3)
t
DVOSC
Data Setup Time Before OSCB
0.75t
CYC
-95
ns
(4)
t
OSCAV
Address Setup Time Before OSCB
0.5t
CYC
-25
-
ns
(5)
t
OSCAX
Address Hold Time After OSCB
0.5t
CYC
-
ns
(6)
t
OSCAX
Data Hold Time After OSCB
10
-
ns
(7)
t
OSCDX
Data Bus Driven From OSCB
(Time to Data Active from High Impedance
State)
.25t
CYC
-25
-
ns
(8)
t
OSCRD
RD, FS Hold Time After OSCB
0.5t
CYC
-
ns
(9)
t
OSCDS
OSCB to DS Propagation Delay
5
25
ns
NOTE:
1. Minimum frequency applies when ALC is high.
Read Cycle Timing (ALC = 1)
(See Figure 3) V
DD
= 5V
DC
±
10%, V
SS
= 0V
DC
, T
A
= -40
o
C to +125
o
C Unless Otherwise Specified.
NUMBER
SYMBOL
PARAMETER
MIN
MAX
UNITS
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