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參數(shù)資料
| 型號： | HIP7010 |
| 廠商： | Intersil Corporation |
| 英文描述： | J1850 Byte Level Interface Circuit |
| 中文描述： | J1850字節(jié)級接口電路 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 106K |
| 代理商： | HIP7010 |
2
Block Diagram
10
9
SOUT
SIN
7
6
5
12
TEST
V
SS
11
CLK
13
14
1
8
STAT
RDY
SCK
IDLE
2
3
VPWOUT
GENERATOR
TIMING
STATE MACHINE
AND CONTROL LOGIC
DECODED VPW IN
OUTPUT DATA
J1850 VPW SYMBOL
ENCODER/DECODER
LSB
MSB
STATUS/CONTROL BYTE
V
DD
4
A
B
C
MUX
CRC GENERATOR/CHECKER
A
B
MUX
DATA SHIFT REGISTER
RESET
SACTIVE
VPWIN
Pin Description
PIN NUMBER
PIN NAME
IN/OUT
PIN DESCRIPTION
1
IDLE
OUT
CMOS Output
2
VPWIN
IN
CMOS Schmitt (No V
DD
Diode)
3
VPWOUT
OUT
CMOS Output
4
V
DD
-
Power Supply
5
RESET
IN
CMOS Schmitt (No V
DD
Diode)
6
TEST
IN
CMOS Input with Pull-Down
7
SACTIVE
OUT
CMOS Output
8
SCK
OUT
Three-State with Pull-Down
9
SOUT
OUT
Three-State with Pull-Down
10
SIN
IN
CMOS Input with Pull-Down
11
V
SS
-
Ground
12
CLK
IN
CMOS Schmitt (No V
DD
Diode)
13
STAT
IN
CMOS Input with Pull-Down
14
RDY
IN
CMOS Input with Pull-Down
HIP7010
相關PDF資料 |
PDF描述 |
|---|---|
| HIP7010B | J1850 Byte Level Interface Circuit |
| HIP7010P | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020 | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AB | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AP | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HIP7010B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Byte Level Interface Circuit |
| HIP7010P | 制造商:Rochester Electronics LLC 功能描述:J1850 JBLIC (DIP) - Bulk |
| HIP7010P WAF | 制造商:Harris Corporation 功能描述: |
| HIP7020 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
| HIP7020 DIE | 制造商:Harris Corporation 功能描述: |
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