參數(shù)資料
型號: HIP5020DB
廠商: HARRIS SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述: 4 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO28
文件頁數(shù): 4/15頁
文件大小: 128K
代理商: HIP5020DB
2-16
Example Application Guide
The HIP5020 provides the flexibility to meet differing needs.
This section illustrates the trade-off of component selection
for three DC-DC converter circuit designs. Each circuit is
optimized for a specific goal: Circuit 1 is optimized for high
efficiency, Circuit 2 is optimized for small size, and Circuit 3
is optimized for low cost. Figure 1 shows the schematic
common to all three converter designs. Table 1 shows the
expected performance parameters for each circuit. Table 2
gives the value of each component referenced in Figure 1.
Table 3 provides a listing of suggested vendors for the major
(or critical) components. Figures 2, 3 and 4 show the
efficiency and transient performance of each circuit.
ERROR AMPLIFIER
Internal Integration Capacitor
12
-
-
pF
Open-Loop Voltage Gain
AV
89
-
-
dB
Gain-Bandwidth Product
GBW
7.2
-
-
MHz
Input Bias Current
I
FB
V
FB
= 1.26VDC
3
-70
70
nA
SOFT START
Current Source
I
SOFT
10
6
14
μ
A
OSCILLATOR
CT Charging Current
126
110
140
μ
A
Initial Frequency Accuracy
±
3
-
-
%
Total Frequency Variation
V
IN
= 4.5 to 18V
±
7
-
±
10
%
PROTECTIVE FUNCTION
Current Limit Threshold
I
O PK
4.5
4
-
A
PWM MODULATOR
Modulator Gain
1.7
-
-
A/V
Minimum On Time
100
-
-
ns
Minimum Off Time
115
-
-
ns
HYSTERETIC COMPARATOR
Propagation Delay
Step V
FB
3
-
-
μ
s
SLOPE GENERATOR
Slope Capacitor Charge Current
I
SLOPE
80
-
-
μ
A
Electrical Specifications
V
IN
= 6.3VDC, Components referenced from Figure 1. TYP values at T
J
= 25
o
C and MIN, MAX limits are for T
J
from 0
o
C to 125
o
C; Unless Otherwise Specified
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
T
J
=
25
o
C
0
o
C < T
J
< 125
o
C
UNITS
TYP
MIN
MAX
HIP5020
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