參數(shù)資料
型號(hào): HIP5020DB
廠商: HARRIS SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述: 4 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO28
文件頁(yè)數(shù): 2/15頁(yè)
文件大?。?/td> 128K
代理商: HIP5020DB
2-14
Functional Block Diagram
R
S
PWM
ERROR
+
AMP
+
CHARGE PUMP
REGULATOR
OVER-CURRENT
PROTECTION
SD
LOWER GATE
DRIVE AND
LOGIC
HYSTERETIC
PHASE
PWM
CURRENT
SENSOR
-
+
-
+
VIN
VCC
BOOT
PHASE
PGND
SOFT
HMI
CP+
CP-
SLOPE
VINF
FB
GND
CT
RUN
OVLD
V
CC
20
μ
A
12pF
+
OSCILLATOR
PWM
LATCH
SLOPE
GENERATOR
MODE
CONTROL
LOGIC
SOFT-
START
REFERENCE
1.26V
+
-
-
-
UPPER GATE
DRIVE
Pin Description
PIN NO
DESIGNATOR
FUNCTION
DESCRIPTION
1, 2, 3
VIN
Input Voltage
Connection to the power source (Battery). Operates from 4.5VDC to 18VDC.
4, 5, 27, 28
PHASE
Switch Node
Connect to output Inductor.
6, 7, 8, 9, 20,
21, 22, 23
PGND
Power Ground
Power Return and thermal interface. Solder these pins to a large copper ground plane.
10
GND
Signal Ground
Connect to the output load return.
11
FB
Voltage Sense
A divider network scales the output voltage to 1.26VDC.
12
VINF
Filtered Input
Connect a low-pass (R-C) filter from V
IN
.
13
HMI
Hysteretic Current
A resistor to the HMI pin sets the peak inductor current level during hysteretic mode.
14
SLOPE
Ramp Set
A capacitor to ground sets the compensation ramp for current mode control.
15
CT
Frequency Set
A capacitor to ground sets the oscillator frequency.
16
BOOT
Bootstrap Bias
A capacitor to Phase pin stores energy for the upper MOSFET drive.
17
VCC
Bias Voltage
Output of charge pump regulator. Use bypass capacitor to ground.
18
CP+
Charge Pump
Capacitor
Connect a capacitor between these pins for the charge pump to generate bias power. The
internal charge pump inverter is synchronized to the oscillator.
19
CP-
24
OVLD
Over-Load
A high level on this pin signals activation of the current limit protection.
25
SOFT
Soft Start
A capacitor to ground sets the soft start interval.
26
SD
Shutdown
A low level suspends operation for a low-dissipation shutdown mode.
HIP5020
相關(guān)PDF資料
PDF描述
HIP5060 ()
HIP5061 FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5061DS FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5062 FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
HIP5062DW FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HIP5020DB WAF 制造商:Harris Corporation 功能描述: 制造商:Intersil Corporation 功能描述:
HIP5020EVAL2 制造商:Harris Corporation 功能描述:
HIP5060 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip PowerSupply
HIP5060D WAF 制造商:Harris Corporation 功能描述:
HIP5060DW 制造商:Harris Corporation 功能描述: