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參數(shù)資料
| 型號： | HHY5W2A6CLF-B |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | HHY5W2A6CLF-B |
HY5W2A6C(L/S)F / HY57W2A1620HC(L/S)T
HY5W26CF / HY57W281620HCT
Rev. 1.2 / Nov. 01
22
Special Operation for Low Power Consumption
Deep Power Down Mode
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole mem-
ory array of the devices.
Data will not be retained once the device enters Deep Power Down Mode.
Full initialization is required when the device exits from Deep Power Down Mode.
Truth Table
Deep Power Down Mode Entry
The Deep Power Down Mode is entered by having /CS and /WE held low with /RAS and /CAS high at the rising edge of the
clock, while CKE is low. The following diagram illustrates deep power down mode entry.
Current State
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
Idle
Deep Power
Down Entry
H
L
L
H
H
L
Deep Power
Down
Deep Power
Down Exit
L
H
X
X
X
X
CLK
CKE
CS
RAS
CAS
WE
tRP
Precharge
if needed
Deep Power Down Entry
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