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參數(shù)資料
| 型號(hào)： | HGTG34N100E2 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 功率晶體管 |
| 英文描述： | LED 5MM VERT SUP DIFF YEL PC MNT |
| 中文描述： | 55 A, 1000 V, N-CHANNEL IGBT, TO-247 |
| 文件頁(yè)數(shù)： | 5/5頁(yè) |
| 文件大?。?/td> | 38K |
| 代理商： | HGTG34N100E2 |
3-128
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HGTG34N100E2
Operating Frequency Information
Operating frequency information for a typical device (Figure
10) is presented as a guide for estimating device performance
for a specific application. Other typical frequency vs collector
current (I
CE
) plots are possible using the information shown
for a typical unit in Figures 7, 8 and 9. The operating
frequency plot (Figure 10) of a typical device shows f
MAX1
or
f
MAX2
whichever is smaller at each point. The information is
based on measurements of a typical device and is bounded
by the maximum rated junction temperature.
f
MAX1
is defined by f
MAX1
= 0.05/t
D(OFF)I
. t
D(OFF)I
deadtime
(the denominator) has been arbitrarily held to 10% of the on-
state time for a 50% duty factor. Other definitions are possible.
t
D(OFF)I
is defined as the time between the 90% point of the
trailing edge of the input pulse and the point where the
collector current falls to 90% of its maximum value. Device
turn-off delay can establish an additional frequency limiting
condition for an application other than T
JMAX
. t
D(OFF)I
is
important when controlling output ripple under a lightly loaded
condition.
f
MAX2
is defined by f
MAX2
= (P
D
- P
C
)/W
OFF
. The allowable
dissipation (P
D
) is defined by P
D
= (T
JMAX
- T
C
)/R
θ
JC
. The sum
of device switching and conduction losses must not exceed P
D
.
A 50% duty factor was used (Figure 10) and the conduction
losses (P
C
) are approximated by P
C
= (V
CE
I
CE
)/2. W
OFF
is
defined as the integral of the instantaneous power loss starting
at the trailing edge of the input pulse and ending at the point
where the collector current equals zero (I
CE
= 0A).
The switching power loss (Figure 10) is defined as f
MAX2
W
OFF
. Turn-on switching losses are not included because they
can be greatly influenced by external circuit conditions and com-
ponents.
Test Circuit
FIGURE 12. INDUCTION SWITCHING TEST CIRCUIT
20V
0V
R
GEN
= 50
1/R
G
= 1/R
GEN
+ 1/R
GE
R
GE
= 50
L = 50
μ
H
V
800V
+
-
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