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參數(shù)資料
| 型號(hào)： | HFA3524IA96 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | 2.5GHz/600MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 172K |
| 代理商： | HFA3524IA96 |
9
Functional Description
The simplified block diagram in Figure 14 shows the 22-bit
data register, two 15-bit R Counters and the 15-bit and 18-bit
N Counters (intermediate latches are not shown). The data
stream is clocked (on the rising edge of Clock) into the DATA
input, MSB first. The last two bits are the Control Bus. The
DATA is transferred into the counters as follows:
Programmable Reference Dividers (IF and RF R Counters)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22-bit shift register into a latch which sets the
15-bit R Counter. Serial data format is shown below.
CONTROL BITS
DATA LOCATION
IR R Counter
RF R Counter
IF N Counter
RF N Counter
C1
0
0
1
1
C2
0
1
0
1
LSB
↓
C1
MSB
↓
R
20
C2
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
R
15
R
16
R
17
R
18
R
19
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
DIVIDE
RATIO
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
32767
NOTES:
8. Divide ratios less than 3 are prohibited.
9. Divide ratio: 3 to 32767.
10. R1 to R15: These bits select the divide ratio of the programmable reference divider.
11. Data is shifted in MSB first.
IF
PRESCALER
15-BIT IF
N COUNTER
15-BIT IF
R COUNTER
15-BIT RF
R COUNTER
18-BIT RF
N COUNTER
OSC
RF
PRESCALER
CHARGE
PUMP
f
OUT
LOCK
DETECT
FASTLOCK
MUX
f
IN
IF
OSC
IN
f
IN
RF
CLOCK
DATA
LE
PHASE
COMP
D
O
IF
LD
RF
PHASE
COMP
D
O
RF
F
O
/LD
CHARGE
PUMP
22-BIT DATA
REGISTER
IF
LD
FIGURE 14. SIMPLIFIED BLOCK DIAGRAM
(Control bits)
Divide ratio of the reference divider, R
Program Modes
HFA3524
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