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參數(shù)資料
| 型號： | HFA3524IA96 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | 2.5GHz/600MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 172K |
| 代理商： | HFA3524IA96 |
10
Programmable Divide (N Counter)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch
(which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data
format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter does not have don’t care bits.
7-Bit Swallow Counter Divide Ratio (A Counter)
Pulse Swallow Function
f
VCO
= [(P x B) + A] x f
OSC
/R
f
VCO
:Output frequency of external voltage controlled
oscillator (VCO)
B:
Preset divide ratio of binary 11-bit programmable
counter (3 to 2047)
A:
Preset divide ratio of binary 7-bit swallow counter
(0
≤
A
≤
127 {RF}, 0
≤
A
≤
15 {IF}, A
≤
B)
f
OSC
:Output frequency of the external reference frequency
oscillator
R:
Preset divide ratio of binary 15-bit programmable
reference counter (3 to 32767)
P:
Preset modulus of dual modulus prescaler
(for IF: P = 8 or 16; for RF: P = 32 or 64)
Programmable Modes
Several modes of operation can be programmed with bits
R16-R19 including the phase detector polarity, charge pump
High Z State and the output of the F
O
/LD pin. The prescaler
and powerdown modes are selected with bits N19 and N20.
The programmable modes are shown in Table 1. Truth table
for the programmable modes and F
O
/LD output are shown in
Table 2 and Table 3.
LSB
↓
C1
MSB
↓
N
20
C2
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
N
12
N
13
N
14
N
15
N
16
N
17
N
18
N
19
(Control bits)
Divide ratio of the programmable divider, N
Program
RF
DIVIDE
RATIO A
N
7
N
6
N
5
N
4
N
3
N
2
N
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
NOTES:
12. Divide ratio 0 to 127.
13. B
≥
A.
IF
DIVIDE
RATIO A
N
7
N
6
N
5
N
4
N
3
N
2
N
1
0
X
X
X
0
0
0
0
1
X
X
X
0
0
0
1
15
X
X
X
1
1
1
1
X = Don’t care condition.
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER
DIVIDE
RATIO B
N
18
N
17
N
16
N
15
N
14
N
13
N
12
N
11
N
10
N
9
N
8
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
2047
1
1
1
1
1
1
1
1
1
1
1
NOTES:
14. Divide ratio 3 to 2047 (divide ratios less than 3 are prohibited).
15. B
≥
A.
TABLE 1. PROGRAMMABLE MODES
C1
C2
R16
R17
R18
R19
R20
0
0
IF Phase
Detector Polarity
IF I
CPO
IF D
O
High Z
IF LD
IF F
O
0
1
RF Phase
Detector Polarity
RF I
CPO
RF D
O
High Z
RF LD
RF F
O
C1
C2
N19
N20
1
0
IF Prescaler
Powerdown IF
1
1
RF Prescaler
Powerdown RF
HFA3524
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