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參數(shù)資料
| 型號： | HFA3524IA96 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | 2.5GHz/600MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 172K |
| 代理商： | HFA3524IA96 |
11
Phase Detector Polarity
Depending upon VCO characteristics, R16 bit should be set
accordingly, (see Figure 15).
When VCO characteristics are positive like (1), R16
should be set HIGH.
When VCO characteristics are negative like (2), R16
should be set LOW.
TABLE 2. MODE SELECT TRUTH TABLE
Φ
D
POLARITY
D
O
HIGH Z STATE
Normal Operation
(NOTE 16)
I
CPO
LOW
IF
PRESCALER
RF
PRESCALER
(NOTE 17)
POWERDOWN
0
Negative
8/9
32/33
Powered Up
1
Positive
High Z State
HIGH
16/17
64/65
Powered Down
NOTES:
16. The I
CPO
LOW current state = 1/4 x I
CPO
HIGH current.
17. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective
f
IN
inputs (to a high impedance state). Powerdown forces the respective charge pump and phase comparator logic to a High Z State condition.
The R counter functionality does not become disabled until both IF and RF powerdown bits are activated. The OSC
IN
pin reverts to a high im-
pedance state when this condition exists. The control register remains active and capable of loading and latching in data during all of the pow-
erdown modes.
TABLE 3. THE F
O
/LD (PIN 10) OUTPUT TRUTH TABLE
RF R [19]
(RF LD)
IF R [19]
(IF LD)
RF R [20]
(RF F
O
)
0
IF R [20]
(IF F
O
)
0
F
O
OUTPUT STATE
0
0
Disabled (Note 18)
0
1
0
0
IF Lock Detect (Note 19)
1
0
0
0
RF Lock Detect (Note 19)
1
1
0
0
RF/IF Lock Detect (Note 19)
X
0
0
1
IF Reference Divider Output
X
0
1
0
RF Reference Divider Output
X
1
0
1
IF Programmable Divider Output
X
1
1
0
RF Programmable Divider Output
0
0
1
1
Fastlock (Note 20)
0
1
1
1
For Internal Use Only
1
0
1
1
For Internal Use Only
1
1
1
1
For Internal Use Only
1
1
1
1
Counter Reset (Note 21)
X = Don’t care condition
NOTES:
18. When the F
O
/LD output is disabled, it is actively pulled to a low logic state.
19. Lock detect output provided to indicate when the VCO frequency is in “l(fā)ock”. When the loop is locked and a lock detect mode is selected, the
pins output is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are both locked.
20. The Fastlock mode utilizes the F
O
/LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation
of Fastlock occurs whenever the RF loop’s lcpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).
21. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits, the N counter resumes counting
in “close” alignment with the R counter. (The maximum error is one prescaler cycle.) If the Reset bits are activated, the R counter is also forced
to Reset, allowing smooth acquisition upon powering up.
(1)
(2)
VCO INPUT VOLTAGE
V
FIGURE 15. VCO CHARACTERISTICS
HFA3524
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