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參數(shù)資料
| 型號： | HFA3524IA96 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | 2.5GHz/600MHz Dual Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 172K |
| 代理商： | HFA3524IA96 |
13
Typical Application Example
Typical Locked Detect Circuit
A lock detect circuit is needed in order to provide a steady
LOW signal when the PLL is in the locked state. A typical cir-
cuit is shown in Figure 20.
100pF
0.01
μ
F
V
P
100pF
0.01
μ
F
V
CC
V
CC
V
P
D
O
IF
18
GND
f
IN
IF
VCO
(NOTE 28)
10pF
IF OUT
CLOCK
DATA
LE
f
IN
IF
15
100pF
FROM
CONTROLLER
R
IN
(NOTE 29)
GND
GND
F
O
/LD
F
O
/LD
OSC
IN
GND
100pF
f
IN
RF
f
IN
RF
R
IN
(NOTE 29)
GND
D
O
RF
V
CC
V
CC
V
P
V
P
CRYSTAL OSCILLATOR
INPUT
100pF
100pF
0.01
μ
F
100pF
0.01
μ
F
VCO
(NOTE 28)
10pF
RF OUT
R2
C4
C3
C2
R1
C1
51
(NOTE 30)
NOTES:
28. VCO is assumed AC coupled.
29. R
IN
increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10
to 200
depending on
the VCO power level. f
IN
RF impedance ranges from 40
to 100
. f
IN
IF impedances are higher.
30. 50
termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and
no terminating resistor is required. OSC
IN
may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own
bias (see Figure 16).
31. Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by
careful board layout.
32. This is a static sensitive device. It should be handled only at static free work stations.
FIGURE 18.
20
19
17
16
14
13
12
11
1
2
3
4
5
6
7
8
9
10
HFA3524
OSC
IN
100k
FIGURE 19.
FIGURE 20.
V
CC
LD
33K
0.01
μ
F
10K
MMBT200
LOCK
DETECT
100K
HFA3524
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