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參數(shù)資料
| 型號(hào)： | HD74CDC587 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 3.3 - V相位鎖3環(huán)路時(shí)鐘驅(qū)動(dòng)器狀態(tài)輸出（3.3 V的鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | HD74CDC587 |
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HD74CDC587
8
Switching Characteristics
LVTTL
(V
REF
= GND, C
L
= 30 pF)
Item
Symbol Min
Typ
Max
Unit
From
(Input)
To
(Output)
Maximum clock frequency f
max
Phase error time
150
—
—
MHz
t
pe
–225
—
+225
ps
CLKIN
↑
FBIN
↑
Between output pins skew t
sk
Jitter
—
—
300
ps
FBOUT / Y
–100
—
+100
ps
CLKIN
↑
Y
↑
Duty cycle
40
—
60
%
Y
Output rise / fall time
t
TLH
t
THL
—
—
2
ns
FBOUT / Y
—
—
2
FBOUT / Y
Note:
The specifications for parameters in this table are applicable only after any appropriate stabilization
time has elapsed.
SSTL_3
(V
REF
= V
TT
= 1.5 V, C
L
= 30 pF)
Item
Symbol Min
Typ
Max
Unit
From
(Input)
To
(Output)
Maximum clock frequency f
max
Phase error time
150
—
—
MHz
t
pe
–300
—
+300
ps
CLKIN
↑
FBIN
↑
Between output pins skew t
sk
Jitter
—
—
300
ps
FBOUT / Y
–75
—
+75
ps
CLKIN
↑
Y
↑
Duty cycle
40
—
60
%
Y
Output rise / fall time
t
TLH
t
THL
—
—
1
ns
FBOUT / Y
—
—
1
FBOUT / Y
Note:
The specifications for parameters in this table are applicable only after any appropriate stabilization
time has elapsed.
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