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參數(shù)資料
| 型號(hào)： | HD74CDC587 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 3.3-V Phase-lock Loop Clock Driver with 3-state Outputs(3.3-V 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 3.3 - V相位鎖3環(huán)路時(shí)鐘驅(qū)動(dòng)器狀態(tài)輸出（3.3 V的鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | HD74CDC587 |
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HD74CDC587
6
Pin Functions
Pin name
No.
I/O
Description
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the
HD74CDC587 clock driver circuit. CLKIN is used to provide the
reference signal to the integrated PLL that generates the clock output
signals. CLKIN must have a fixed frequency and fixed phase for the
PLL to obtain phase lock. Once the circuit is powered up and a valid
CLKIN signal is applied, a stabilization time is required for the PLL to
obtain phase-lock of its feedback signal to its reference signal.
FBIN
3
I
Feedback input. FBIN provides the feedback signal to the internal
PLL. FBIN should be wired to FBOUT. The integrated PLL adjusts
the output clocks to obtain zero phase delay between FBIN and
CLKIN.
V
REF
2
I
Voltage reference. V
is the reference voltage required for SSTL
operation. A nominal voltage of 1.5 V should be applied when SSTL
operation of CLKIN and FBIN is required. If V
is strapped to GND,
CLKIN and FBIN operate at TTL switching levels.
Output enable.
OE
is the output enable for all of the Y outputs.
When
OE
is low, all Y outputs are enabled. When
OE
is high, all Y
outputs are in the high impedance state. FBOUT is not disabled by
OE
; therefore, the PLL is not disrupted when the Y outputs are placed
into the high impedance state.
OE
30
I
TEST
31
I
Test input. TEST is used to bypass the PLL circuitry for factory
testing of the device. When TEST is low, all outputs operate using
the PLL circuitry. When TEST is high, the device is placed in a test
mode that bypasses the PLL circuitry.
Reset input.
RESET
is used to reset the counter circuit that divides
the VCO output frequency. Y outputs configured as 1
×
of the input
signal may be reset to a known state.
RESET
is a negative edge
triggered signal. When a high to low edge occurs at
RESET
, the
counter that divides the VCO output signal is asynchronously cleared
to a low level. For normal operation, a high level signal should be
maintained on the
RESET
input.
RESET
32
I
SEL(0:3)
28–25
I
Select input. All SEL(0:3) inputs must be permanently tied to logic
low for normal operation.
1Y(0:3)
2Y(0:3)
3Y(0:3)
4Y(0:3)
8, 9, 12, 13
16, 17, 20, 21
36, 37, 40, 41
44, 45, 48, 49
O
Clock outputs. All outputs operate at 1
×
the input clock (CLKIN)
frequency. The duty cycle of the Y output signals is nominally 50%,
independent of the duty cycle of CLKIN.
FBOUT
5
O
Feedback output. FBOUT is synchronized in phase and frequency to
the input clock. FBOUT is not a 3-state output and is not disabled
when
OE
is asserted low. A stabilization time is required on power up
and the application of a fixed frequency, fixed-phase signal at CLKIN.
In addition, a stabilization time may be required after changes are
made to the SEL(0:3) inputs, the TEST input, or changes to the input
frequency at CLKIN.
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