參數(shù)資料
型號(hào)： HD66760
廠商： Hitachi,Ltd.
英文描述： 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors
中文描述： 104 × 80點(diǎn)圖形LCD控制器/驅(qū)動(dòng)器的256色
文件頁(yè)數(shù)： 43/105頁(yè)
文件大小： 653K
代理商： HD66760
HD66760
43
Serial Data Transfer (I2C bus interface)
Setting the IM2=Vcc and IM1=Vcc level allows I2C bus interface, using the serial data line (SDA) and serial
transfer clock line (SCL). For the I2C bus interface, the IM0/ID pin function uses an ID pin.
The HD66760W is initiated serial data transfer by transferring the first byte when a high SCL level at the
falling edge of the SDA input is sampled; it ends serial data transfer when a high SCL level at the rising edge
of the SDA input is sampled.
Table 29 illustrates the start byte of I2C bus interface data and Figure 29 and 30 show the I2C bus interface
timing sequence.
The HD66760W is selected when the higher 6-bit slave address in the first byte transferred from the master
device match the 6-bits device identification code assigned to the HD66760W. The HD66760W, when
selected, receive the subsequent data string. The lower 1-bit of the device identification code can be
determined by the ID pin; select an appropriate code that is not assigned to any other slave device. The upper
five bits are fixed to 01110. One slave address is assigned to a single HD66760W.
The ninth bit of the first byte is a receive-data acknowledge bit (ACK). When the received slave address
matches the device ID code, HD66760W pulls down the ACK bit to a low level. Therefore, the ACK output
buffer is an open-drain structure, only allowing low-level output. However, the ACK bit is undermined
immediately after power-on; make sure to initialize the LSI using the RESET* input.
After identifying the address in the first byte, the HD66760W receives the subsequent data as an HD66760W
index or as RAM data. Having received 8-bit data normally, HD66760W pulls down the ninth bit (ACK) to a
low level. The index register or RAM data is 16-bits data format. Therefore data transfer has to be two 8-bit
access cycles after first byte transfer.
Five bytes of GRAM read data after the start byte are invalid. The HD66760W start to read correct GRAM
data from sixth byte.
Table 29 Start Byte Format
Transfer Bit
S
1
2
3
4
5
6
7
8
9
Start byte format
Transfer start
Device ID code
RS
R/W
ACK
0
1
1
1
0
ID
Note:
ID bit is selected by the IM0/ID pin.
Table 30 RS and R/W bit function
RS
R/W
Function
0
0
Write index register to index
0
1
Reads status
1
0
Write control register or GRAM via write data register
1
1
Read GRAM via read data register
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