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參數(shù)資料
| 型號： | HCD404669 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit(帶雙音多頻電路的低電壓微計算機) |
| 中文描述： | 低電壓如同在微機芯片的DTMF產(chǎn)生電路（帶雙音多頻電路的低電壓微計算機） |
| 文件頁數(shù)： | 86/142頁 |
| 文件大?。?/td> | 894K |
| 代理商： | HCD404669 |
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HD404669 Series
86
Notes on Use:
Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register 1A (SM1A: $005) again.
Serial 1 interrupt request flag (IFS1: $003, bit 2) set: If the state is changed from transfer to another by
writing to serial mode register 1A (SM1A: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag 1 (IFS1: $003, 2) is not set. To set the serial
interrupt request flag, serial mode register 1A (SM1A: $005) write or STS instruction execution must be
programmed to be executed after confirming that the
SCK
1
pin is at 1, that is, after executing the input
instruction to port R4.
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
Serial Mode Register 1A (SM1A: $005)
Serial Mode Register 1B (SM1B: $028)
Serial Data Register 1 (SR1L: $006, SR1U: $007)
Port Mode Register A (PMRA: $004)
Miscellaneous Register (MIS: $00C)
Serial Mode Register 1A (SM1A: $005):
This register has the following functions (figure 62).
R4
1
/
SCK
1
pin function selection
Transfer clock selection
Prescaler division ratio selection
Serial interface initialization
Serial mode register 1A (SM1A: $005) is a 4-bit write-only register. It is reset to $0 by an MCU reset or
when the MCU switches to stop mode.
A write signal input to serial mode register 1A (SM1A: $005) discontinues the input of the transmit clock
to the serial data register 1 (SR1L: $006, SR1U: $007) and octal counter, and the octal counter is reset to
000. Therefore, if a write is performed during data transfer, the serial 1 interrupt request flag (IFS1: $003,
bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.
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