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參數(shù)資料
| 型號： | HCD404669 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit(帶雙音多頻電路的低電壓微計算機) |
| 中文描述： | 低電壓如同在微機芯片的DTMF產(chǎn)生電路（帶雙音多頻電路的低電壓微計算機） |
| 文件頁數(shù)： | 45/142頁 |
| 文件大?。?/td> | 894K |
| 代理商： | HCD404669 |
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HD404669 Series
45
Input/Output
The MCU has 47 input/output pins (D
0
to D
5
, D
9
to D
11
, R0
0
to R4
3
and R6
0
to RA
1
) and 5 input pins (D
12
,
D
13
, RD
0
, RD
1
and RE
0
). The features are described below.
Four pins D
0
to D
3
are high source current (10 mA maximum) input/output pins.
Five pins D
4
, D
5
, and D
9
to D
11
are high sink current (15 mA maximum) input/output pins.
Certain of these input and output pins have shared functions with timers, the serial interface, and other
peripheral functions. The D
12
, D
13
, R0, R3
0
, R3
2
, R4, RD
0
, RD
1
and RE
0
pins are shared function pins.
The use of these pins as peripheral function pins takes precedence over their use as the D and R port
pins. Pins that are set to function as peripheral function pins are switched automatically between their
various functions and between the input and output directions according to their specifications under the
peripheral function setting.
Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.
Peripheral function output pins are all CMOS outputs. However, the SO
1
pin and the R4
3
port pin can be
set to function as NMOS open drain outputs by software.
Since the MCU goes to the reset state internally after a reset and in stop mode, the peripheral function
settings for these pins are cleared. Furthermore, since the data control registers (DCD and DCR) are
also reset, the input/output pins go to the high-impedance state.
The D
0
to D
3
pin circuits include pull-down MOS transistors, and all the other pin circuits include pull-
up MOS transistors. Note that the on/off states of the pull-up and pull-down MOS transistors can be set
independently of the setting for use as peripheral function pins.
I/O buffer configurations are shown in figures 27 and 28, and I/O pin circuit structures are listed in tables
14 and 15.
V
CC
V
CC
Pull-up control signal
Buffer control signal
Output data
Input data
HLT
MIS3
DCD,DCR
PDR
Input control signal
Pull-up MOS
Figure 27 I/O Buffer Configuration (with Pull-Up MOS)
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