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參數(shù)資料
| 型號： | HCD404669 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit(帶雙音多頻電路的低電壓微計(jì)算機(jī)) |
| 中文描述： | 低電壓如同在微機(jī)芯片的DTMF產(chǎn)生電路（帶雙音多頻電路的低電壓微計(jì)算機(jī)） |
| 文件頁數(shù)： | 41/142頁 |
| 文件大?。?/td> | 894K |
| 代理商： | HCD404669 |
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HD404669 Series
41
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 23. As shown in table 13, a ceramic
oscillator or crystal oscillator can be connected to OSC
1
and OSC
2
, and a 32.768-kHz oscillator can be
connected to X1 and X2. The system oscillator can also be operated by an external clock. Set bits 0 and 1
(SSR10, SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22, SSR23) of system
clock select register 2 (SSR2: $02A) according to the frequency of the oscillator connected to OSC
1
and
OSC
2
(figures 24 and 25).
The system clock division ratio can be set with bits 0 and 1 (SSR20, SSR21) of system clock select register
2 (SSR2: $02A). The value set in these bits does not become valid until watch mode is entered. Therefore,
the system clock must be halted temporarily when changing the division ratio.
The system clock division ratio immediately after a reset or when stop mode is cleared can be selected by
means of the SEL pin level, division-by-4 being selected when the SEL pin is at Vcc potential, and
division-by-32 when at GND potential.
Note:
If the system clock select register 1 and 2 (SSR1, SSR2: $029, $02A) setting does not match the
oscillator frequency, DTMF generation circuit and subsystems using the 32.768-kHz oscillation
will malfunction.
OSC
2
OSC
1
X1
X2
System
clock
oscillator
Sub-
system
clock
oscillator
1/4, 1/8,
1/16 or
1/32
division
circuit
Timing
generation
circuit
System
clock
selection
circuit
CPU with ROM,
RAM, registers,
flags, and I/O
Internal
Peripheral
module
interrupts
Time base
interrupt
Time-base
clock
selection
circuit
1/8 or 1/4
division
circuit
Timing
generation
circuit
Timing
generation
circuit
1/8
division
circuit
f
W
t
Wcyc
f
SUB
t
subcyc
LSON
TMA3 bit
f
cyc
t
cyc
f
OSC
f
X
CPU
PER
CLK
Figure 23 Clock Generation Circuit
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