- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385354 > HC273 (System Logic Semiconductor Co., Ltd.) Octal D Flip-Flop with Common Clock and Reset PDF資料下載
參數(shù)資料
| 型號(hào)： | HC273 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | Octal D Flip-Flop with Common Clock and Reset |
| 中文描述： | 八路D觸發(fā)器與普通時(shí)鐘和復(fù)位拖鞋 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 49K |
| 代理商： | HC273 |
SL74HC273
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
5.0
24
28
4.0
20
24
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q (Figures
1 and 4)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
t
PHL
Maximum Propagation Delay , Reset to Q (Figures
2 and 4)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC
2
f+I
CC
V
CC
48
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
SU
Minimum Setup Time, Data to
Clock (Figure 3)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
h
Minimum Hold Time, Clock to
Data (Figure 3)
2.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns
t
rec
Minimum Recovery Time,
Reset Inactive to Clock (Figure
2)
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
t
w
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
r,
t
f
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HC365 | Hex 3-State Noninverting Buffer with Common Enables |
| HC4046 | Phase-Locked Loop |
| HC4053 | IC-VLTG REG 125V-1A |
| HC4094 | T-NPN-SI HIGH VLTG AMP |
| HC49J | SM Crystal Formed Leads |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HC277-M40 | 制造商:Leviton Manufacturing Co 功能描述: |
| HC277-M53 | 制造商:Leviton Manufacturing Co 功能描述: |
| HC-278 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hybrid Assemblies OPTIC RECEIVER MODULES |
| HC-278M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hybrid Assemblies OPTIC RECEIVER MODULES |
| HC280-04V1 | 制造商:PREMO 制造商全稱:PREMO CORPORATION S.L 功能描述:Common mode chokes with Nanocrystalline cores & Common mode chokes with Ferrite cores - SMD format |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。