參數(shù)資料
型號: HB52RF648DC-B
廠商: Elpida Memory, Inc.
英文描述: 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 】 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M 】 8 components) PC133/100 SDRAM
中文描述: 512 MB的無緩沖內(nèi)存的SODIMM 64 Mword】64位,133/100 MHz內(nèi)存總線,2銀模塊(16個32米】8部分)PC133/100 SDRAM內(nèi)存
文件頁數(shù): 16/20頁
文件大?。?/td> 160K
代理商: HB52RF648DC-B
HB52RF648DC-B, HB52RD648DC-B
Data Sheet E0083H40
16
Relationship Between Frequency and Minimum Latency
HB52RF648DC/
HB52RD648DC
Parameter
-75
-A6/B6
Frequency (MHz)
133
100
t
CK
(ns)
Active command to column command
(same bank)
Symbol
PC100
Symbol 7.5
10
Notes
l
RCD
3
2
1
Active command to active command
(same bank)
l
RC
9
7
= [l
RAS
+ l
RP
]
1
Active command to precharge command
(same bank)
l
RAS
6
5
1
Precharge command to active command
(same bank)
l
RP
3
2
1
Write recovery or data-in to precharge
command (same bank)
l
DPL
Tdpl
2
2
1
Active command to active command
(different bank)
l
RRD
2
2
1
Self refresh exit time
l
SREX
l
APW
Tsrx
1
1
2
Last data in to active command
(Auto precharge, same bank)
Tdal
5
4
= [l
DPL
+ l
RP
]
Self refresh exit to command input
l
SEC
9
7
= [l
RC
]
3
Precharge command to high impedance
(
CE
latency = 2)
(
CE
latency = 3)
l
HZP
l
HZP
l
APR
Troh
2
2
Troh
3
3
Last data out to active command
(Auto precharge, same bank)
1
1
Last data out to precharge (early precharge)
(
CE
latency = 2)
(
CE
latency = 3)
l
EP
l
EP
l
CCD
l
WCD
l
DID
l
DOD
l
CLE
l
RSA
1
1
2
2
Column command to column command
Tccd
1
1
Write command to data in latency
Tdwd
0
0
DQMB to data in
Tdqm
0
0
DQMB to data out
Tdqz
2
2
CKE to CK disable
Tcke
1
1
Register set to active command
Tmrd
1
1
相關(guān)PDF資料
PDF描述
HB52RD648DC-B 512 MB Unbuffered SDRAM S.O.DIMM 64-Mword 】 64-bit, 133/100 MHz Memory Bus, 2-Bank Module (16 pcs of 32 M 】 8 components) PC133/100 SDRAM
HB52RF649DC 512MB Unbuffered SDRAM S.O.DIMM
HB52RD649DC-A6B 512MB Unbuffered SDRAM S.O.DIMM
HB52RD649DC-A6BL 512MB Unbuffered SDRAM S.O.DIMM
HB52RD649DC-B 512MB Unbuffered SDRAM S.O.DIMM
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參數(shù)描述
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