參數(shù)資料
型號： H1A424M167
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 模擬信號調(diào)理
英文描述： Image Signal Processor for Hyundai CMOS Image Sensor
中文描述： SPECIALTY ANALOG CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-64
文件頁數(shù)： 3/47頁
文件大小： 374K
代理商： H1A424M167
Hyundai Electronics Industries Co., Ltd.
H1A424M167
1999 October 11 Page 3
T ABLE OF CONT ENT S
1. FEATURES......................................................................................................................................5
2. PIN CONFIGURATION..................................................................................................................6
3. PIN DEFINITION............................................................................................................................7
4. SYSTEM DIAGRAM.....................................................................................................................10
5. BLOCK DIAGRAM ......................................................................................................................10
6. VIDEO PROCESSING ENGINE BLOCK DIAGRAM...............................................................11
7. FUNCTIONAL DESCRIPTION....................................................................................................12
7.1. H
OST
I
NTERFACE
.......................................................................................................................12
7.1.1. Serial Interface..................................................................................................................12
7.1.2. Host Parallel Interface ......................................................................................................14
7.1.3. Serial or Parallel Interface selection .................................................................................15
7.2. C
LOCK
(MCLK, PCLK, VCLK) T
IMING
D
IAGRAM
.....................................................................16
7.3. V
IDEO
O
UTPUT
I
NTERFACE
.........................................................................................................16
7.4. R
ELATIONS BETWEEN INPUT VIDEO TIMING AND OUTPUT VIDEO TIMING
........................................17
7.4.1. VGA...................................................................................................................................18
7.4.2. CIF....................................................................................................................................18
7.4.3. SIF.....................................................................................................................................19
7.4.4. QCIF.................................................................................................................................19
7.4.5. QSIF..................................................................................................................................20
8. REGISTER DESCRIPTION .........................................................................................................21
8.1. R
EGISTERS
M
NEMONIC
T
ABLE
....................................................................................................21
8.2. BASE R
EGISTER
M
AP
................................................................................................................24
8.2.1. Normal Register[80h~83h]................................................................................................24
8.2.2. Color Matrix Coefficients Value[8Ah ~ 95h].....................................................................26
8.3. AUTO R
EGISTER
M
AP
...............................................................................................................29
8.3.1. Function Enable Register[A0h].........................................................................................29
8.3.2. AWB/AE Windows Configuration Registers[A1h~A6h]......................................................30
8.3.3. Normal Register[A7h~B8h]...............................................................................................31
8.4. OUT R
EGISTER
M
AP
..................................................................................................................37
8.4.1. Normal Register[C0h~C2h]...............................................................................................37
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