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| 型號： | H1A424M167 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Image Signal Processor for Hyundai CMOS Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 15/47頁 |
| 文件大?。?/td> | 374K |
| 代理商： | H1A424M167 |
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Hyundai Electronics Industries Co., Ltd.
H1A424M167
1999 October 11 Page 15
ALE
IOW
AD[7:0]
A[7:0]
D[7:0]
Stretched
Stretched
IODone
CSB
Active write operation
Host Parallel Write Operation
Similar to parallel read operation, parallel write operation needs
only 1 operation cycle.
The host must watch ‘IODone’ signal for a proper write operation. IODone signal
indicates the completion of read/write operation. So the host must hold the IOW, CSB,
Write Data[7:0] signals until IODone signal become active. When IODone signal
become active, ISP accept the write data internally. At the final stage, the host ends the
bus cycle(CSB, IOW, Write Data[7:0]) and IODone signal become inactive.
ISP holds IODone active until read/write operation is completed. CIS register read/write
operation needs more time than ISP register read/write operation. So IODone active
signal for CIS register read/write operation is much longer than that of ISP register
read/write operation.
7.1.3. Serial or Parallel Interface selection
The selection between serial interface and parallel interface is made at hardware reset
time. If CSB/MODE pin, pin number 64, is pulled down during reset, Serial Interface is
configured, and otherwise parallel interface is selected.
For example, Serial Interface selection timing is as below.
RESETB
CSB/MODE
More than 64 MCLK
Serial Interface Selection
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