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| 型號(hào)： | H1A424M167 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Image Signal Processor for Hyundai CMOS Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 12/47頁 |
| 文件大?。?/td> | 374K |
| 代理商： | H1A424M167 |
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Hyundai Electronics Industries Co., Ltd.
H1A424M167
1999 October 11 Page 12
7. Functional Description
7.1. Host Interface
Hyundai ISP chip supports two kinds of host interface, serial and 8bit parallel, to
program ISP registers or to read ISP registers. And the host interface is also used to
write or to read CMOS Image Sensor(CIS) registers through ISP.
7.1.1. Serial Interface
The serial interface of Image Signal Processor[ISP] is implemented by the following
pins.
SCLK: Serial Clock SDATA: Serial Data
7.1.1.1. WRITE OPERATION
Write transaction between the ISP and a host is the similar as the well-known I2C serial
interface except that only one byte transfer at each transaction is allowed. The
transaction consists of START CONDITION, DEVICE ADDR + R/W[0], SUB ADDR,
WRITE DATA, and STOP CONDITION states. The single write access sequence is as
follows.
S DEVICE ADDR A1 SUB ADDR A2 WRITE DATA A3 P
[ S ]
[ DEVICE ADDR ]
Operation start condition
ISP
40h
(010_0000 + 0), CIS
22h
(001_0001 + 0)
e
device address + R/W bit
Acknowledge from ISP
ISP Sub address space 80h ~ FFh
CIS Sub address space 00h ~ 7Fh
Acknowledge from ISP
Register Value from host
Acknowledge from ISP
Operation stop condition
[ A1 ]
[ SUB ADDR ]
[ A2 ]
[ WRITE DATA ]
[ A3 ]
[ P ]
7.1.1.2. READ OPERATION
Read transaction between the ISP and a host proceeds as the following sequence.
START CONDITION
e
DEVICE ADDR + R/W[0]
e
SUB ADDR
e
START
CONDITION
e
DEVICE ADDR + R/W[1]
e
READ DATA
e
STOP CONDITION
The ISP register access throughput is one byte at each read transaction.
But the
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