參數(shù)資料
型號(hào)： GT3200-JD
廠商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： Aluminum Electrolytic Radial Leaded General Purpose Capacitor; Capacitance: 33uF; Voltage: 16V; Case Size: 5x11 mm; Packaging: Bulk
中文描述： DATACOM, INTERFACE CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, 0.5 MM PITCH, TQFP-64
文件頁(yè)數(shù)： 40/51頁(yè)
文件大小： 1462K
代理商： GT3200-JD
USB2.0 PHY IC
Revision 1.3 (10-05-04)
35
SMSC GT3200, SMSC USB3250
DATASHEET
Note 8.3
T0 may be up to 4ms after HS Reset T0.
Note 8.4
The SIE must use LINESTATE to detect the downstream port chirp sequence.
Note 8.5
Due to the assertion of the HS termination on the host port and FS termination on the
device port, between T1 and T7 the signaling levels on the bus are higher than HS
signaling levels and are less than FS signaling levels.
8.10
HS Detection Handshake - Suspend Timing
If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are
assumed to be powered down.
Figure 8.6
shows how CLK60 is used to control the duration of the
chirp generated by the device.
When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE),
SUSPENDN is combinatorially negated at time T0 by the SIE. It takes approximately 5 milliseconds
for the transceiver's oscillator to stabilize. The device does not generate any transitions of the CLK60
signal until it is "usable" (where "usable" is defined as stable to within ±10% of the nominal frequency
and the duty cycle accuracy 50±5%).
The first transition of CLK60 occurs at T1. The SIE then sets OPMODE to Disable Bit Stuffing and
NRZI encoding, XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLK60 cycles to
ensure a 1ms minimum duration. If CLK60 is 10% fast (66MHz) then Chirp K will be 1.0ms. If CLK60
is 10% slow (54 MHz) then Chirp K will be 1.2ms. The 5.6ms requirement for the first CLK60 transition
after SUSPENDN, ensures enough time to assert a 1ms Chirp K and still complete before T3. Once
the Chirp K is completed (T3) the SIE can begin looking for host chirps and use CLK60 to time the
process. At this time, the device follows the same protocol as in section 8.9 for completion of the High
Speed Handshake.
T9
The earliest time at which host port may end reset.
The latest time, at which the device may remove the
DP pull-up and assert the HS terminations, reverts to
HS default state.
HS Reset T0 + 10ms
Table 8.7 Reset Timing Values (continued)
TIMING
PARAMETER
DESCRIPTION
VALUE
相關(guān)PDF資料
PDF描述
GT3200-JN USB2.0 PJY IC
GT3200-JV USB2.0 PJY IC
GTF701-HS3 2-Line EMI-Filter with ESD -Protection
GTF701-HS3-GS08 2-Line EMI-Filter with ESD -Protection
GTO1200-2R Snubber Capacitors, Dry Self-healing
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GT3200-JN 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:USB2.0 PJY IC
GT3200-JV 制造商:Microchip Technology 功能描述:PHY 1-CH 12Mbps/480Mbps
GT3-2024SCF 制造商:Hirose 功能描述:
GT3-2024SCF(70) 制造商:Hirose 功能描述:
GT-32090-A0-PBN-C000 制造商:Marvell 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*