參數(shù)資料
型號(hào)： GT3200-JD
廠商： STANDARD MICROSYSTEMS CORP
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： Aluminum Electrolytic Radial Leaded General Purpose Capacitor; Capacitance: 33uF; Voltage: 16V; Case Size: 5x11 mm; Packaging: Bulk
中文描述： DATACOM, INTERFACE CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, 0.5 MM PITCH, TQFP-64
文件頁(yè)數(shù)： 25/51頁(yè)
文件大?。?/td> 1462K
代理商： GT3200-JD
USB2.0 PHY IC
SMSC GT3200, SMSC USB3250
20
Revision 1.3 (10-05-04)
DATASHEET
bit then the byte boundary can be stretched to 45 CLK60 cycles, and two stuffed bits would result in
a 50 CLK60 cycles.
Figure 7.2
shows the relationship between CLK60 and the transmit data transfer signals in FS mode.
TXREADY is only asserted for one CLK60 per byte time to signal the SIE that the data on the TXDATA
lines has been read by the Macrocell. The SIE may hold the data on the TXDATA lines for the duration
of the byte time. Transitions of TXVALID must meet the defined setup and hold times relative to
CLK60.
Figure 7.3
shows the relationship between CLK60 and the receive data control signals in FS mode.
RXACTIVE "frames" a packet, transitioning only at the beginning and end of a packet. However
transitions of RXVALID may take place any time 8 bits of data are available.
Figure 7.3
also shows
how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be
presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing
relationship is applied to the data and control signals.
7.3
Clock and Data Recovery Circuit
This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer. The Elasticity
Buffer is used to compensate for differences between the transmitting and receiving clock domains.
The USB2.0 specification defines a maximum clock error of ±1000ppm of drift.
Figure 7.2 FS CLK Relationship to Transmit Data and Control Signals (8-bit mode)
Figure 7.3 FS CLK Relationship to Receive Data and Control Signals (8-bit mode)
CLKOUT
TXDATA[7:0]
TXVALID
TXREADY
Care
DATA3
PID
DATA4
DATA1
DATA2
DATA(n+1)
DATA(n+2)
CLK60
RXACTIVE
RXDATA[7:0]
RXVALID
DATA(n)
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