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參數(shù)資料
| 型號： | GT3200-JD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Aluminum Electrolytic Radial Leaded General Purpose Capacitor; Capacitance: 33uF; Voltage: 16V; Case Size: 5x11 mm; Packaging: Bulk |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.5 MM PITCH, TQFP-64 |
| 文件頁數(shù)： | 30/51頁 |
| 文件大?。?/td> | 1462K |
| 代理商： | GT3200-JD |
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USB2.0 PHY IC
Revision 1.3 (10-05-04)
25
SMSC GT3200, SMSC USB3250
DATASHEET
Note 7.2
Figure 7.10
,
Figure 7.11
and
Figure 7.12
are timing examples of a HS/FS Macrocell when
it is in HS mode. When a HS/FS Macrocell is in FS Mode (8-bit mode) there are
approximately 40 CLK60 cycles every byte time. The Receive State Machine assumes that
the SIE captures the data on the RXDATA bus if RXACTIVE and RXVALID are asserted.
In FS mode, RXVALID will only be asserted for one CLK60 per byte time.
Note 7.3
Figure 7.10
,
Figure 7.11
and
Figure 7.12
the SYNC pattern on DP/DM is shown as one
byte long. The SYNC pattern received by a device can vary in length. These figures
assume that all but the last 12 bits have been consumed by the hubs between the device
and the host controller.
Figure 7.10 Receive Timing for Data (with CRC-16 in 8-bit mode)
Figure 7.11 Receive Timing for Setup Packet (8-bit mode)
CLK60
RXACTIVE
RXDATA[7:0]
RXVALID
RXERROR
DP/DM
SYNC
PID
EOP
PID
CLK60
RXACTIVE
RXDATA[7:0]
RXVALID
RXERROR
DP/DM
CRC-5 Computation
SYNC
PID
DATA
DATA
EOP
PID
DATA
DATA
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