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參數(shù)資料
| 型號： | GS9023ACFY |
| 廠商： | Gennum Corporation |
| 元件分類： | Codec |
| 英文描述： | GENLINX -TM II GS9023A Embedded Audio CODEC |
| 中文描述： | GENLINX -商標二GS9023A嵌入式音頻編解碼器 |
| 文件頁數(shù)： | 19/37頁 |
| 文件大?。?/td> | 318K |
| 代理商： | GS9023ACFY |
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G
GENNUM CORPORATION
19795 - 6
The arbitrary data packet words are defined as follows:
ADF: Ancillary Data Flag.
The ancillary data flag marks the
beginning of an ancillary packet and is automatically
generated by the GS9023A.
DID: Data ID.
Configured in “PKTID[7:0]” of Host Interface
Register #5h. The two most significant bits are internally
generated by the GS9023A.
SDID: Secondary Data ID.
The Secondary Data ID is
handled as user input data.
DC: Data Count.
The data count represents the number of
user data words to follow, up to a maximum of 255 words.
The data count is handled as user input data. For the
GS9023A the maximum data count is 253 since the total
number of words that can be input is 255 less the SDID and
DC words.
UDW: User Data Word.
CS: Checksum.
The checksum consists of nine bits. The
checksum is used to determine the validity of the words
data ID through user data. It is the sum of the nine least
significant bits of the words data ID through user data. The
checksum is automatically generated by the GS9023A.
2.1.11 Error Detection
The GS9023A provides error status information in Host
Interface Register #7h as described in Table 14. All errors
are cleared when Host Interface Register #7h is read.
2.2 DEMULTIPLEX MODE
2.2.1 Video Clock Input
A master video clock must be supplied to the PCLK pin
corresponding to the selected video signal. The supported
video input standards and corresponding clock frequencies
are listed in Table 1.
2.2.2 Video Data Input
The video data DIN[9:0] is clocked in to the GS9023A on
the rising edge of PCLK. The video clock frequency must
correspond to the video input standard selected. This can
be done with the VM[2:0] and TRS input pins or selected
via the “VSEL” bit of Host Interface Register #0h. When
“VSEL” is set HIGH, the video input standard is selected by
“VMOD[2:0]” and “D2_TRS” in Host Interface Register #0h.
The supported video input standards are listed in Table 1.
After the user has specified the video input standard via the
VM[2:0] and TRS pins or in Host Interface Register #0h, the
GS9023A performs video standard detection to verify that
the input video stream corresponds to the selected
standard. The GS9023A then performs a ‘lock’ procedure,
as selected by the “ACTSEL” bit of Host Interface Register
#4h, to determine if the audio is synchronous to the video.
When “ACTSEL” is LOW, the GS9023A counts the number
of audio samples present in a frame or multiple frames,
depending on the video standard selected. ‘Lock’ is
achieved if the required number of samples are detected
for 48kHz synchronous audio. When “ACTSEL” is HIGH, the
GS9023A ‘locks’ by detecting the presence of an audio
control packet corresponding to the DID configured in
“ACID[3:0]” of Host Interface Register #4h and occurring at
the expected line and position as listed in Table 6. If the
video signal does not contain audio control packets, ‘lock’
will not occur. Once ‘lock’ is achieved the LOCK output pin
and the “LOCK” bit of Host Interface Register #0h are set
HIGH and audio demultiplexing begins. The LOCK output
pin and the “LOCK” bit stay active regardless of the number
of samples in the video stream after ‘lock’ is achieved. The
GS9023A drops out of ‘lock’ when there are no more
packets detected in the video stream.
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| GS9023-CFY | Aluminum Electrolytic Radial Leaded Bi-Polar Capacitor; Capacitance: 100uF; Voltage: 63V; Case Size: 12.5x20 mm; Packaging: Bulk |
| GS9024 | Automatic Cable Equalizer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| GS9023ACFYE3 | 制造商:Semtech Corporation 功能描述:Audio Codec 4ADC / 4DAC 24-Bit 100-Pin LQFP |
| GS9023B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Embedded Audio CODEC |
| GS9023BCVE3 | 功能描述:IC AUDIO CODEC 100PIN TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| GS9023-CFY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Embedded Audio CODEC |
| GS9024 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Automatic Cable Equalizer |
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