參數(shù)資料
型號： GS9023ACFY
廠商： Gennum Corporation
元件分類： Codec
英文描述： GENLINX -TM II GS9023A Embedded Audio CODEC
中文描述： GENLINX -商標二GS9023A嵌入式音頻編解碼器
文件頁數(shù)： 7/37頁
文件大?。?/td> 318K
代理商： GS9023ACFY
7 of 37
G
GENNUM CORPORATION
19795 - 6
72-74, 77-81
DATA[0:7]
I/O
Host Interface data bus. DATA[7] is the MSB and DATA[0] is the LSB.
83
RE
I
Read enable for Host Interface. Active LOW.
84
WE
I
Write enable for Host Interface. Active LOW.
85
CS
I
Chip select for Host Interface. Active LOW.
86-89
ADDR[3:0]
I
Host Interface address bus. ADDR[3] is the MSB and ADDR[0] is the LSB.
91
ANCI
I
ANCI Selection. Valid in Demultiplex Mode only. When set HIGH, each ancillary
data packet with a DID corresponding to either the audio packet DID, the
extended audio packet DID or the arbitrary packet DID is removed from the
video signal. The data contained in the packets are output at the corresponding
pins. The various DIDs are user programmable in the internal registers and are
accessible via the Host Interface.
NOTE: When ancillary data packets are deleted, the GS9023A does not
recalculate the EDH checkwords.
When set LOW, all ancillary data packets remain in the video signal.
92
TRS
I
TRS Selection. Used in conjunction with the VM[2:0] pins to select video
standard format. In Multiplex Mode, when the TRS pin is HIGH, TRS is added to a
composite video signal. In Demultiplex Mode, when HIGH, TRS is removed from
a composite video signal. See Table 1.
93
EDH_INS
I
EDH Insert Selection. Valid in Multiplex Mode only. When set HIGH, the GS9023A
performs EDH functions according to SMPTE RP165. When set LOW, EDH is not
inserted. This setting is logical OR with the related EDHON setting in host
interface register address 1h.
NOTE: Active picture and full field data words are updated from recalculated
values but error flag information is replaced with the values programmed in the
internal registers via the Host Interface.
94
MUTE
I
Audio mute. In Multiplex Mode, when set HIGH, the embedded audio packets
are forced to ‘0’. In Demultiplex Mode, when set HIGH, the output data is forced
to “0”. This setting is logical OR with the related MUTE setting in host interface
address 4h.
95-97
AM[2:0]
I
Audio mode format. In Multiplex Mode, AM[2:0] indicates the input audio data
format. In Demultiplex Mode, AM[2:0] indicates the output audio data format.
AM[2] is the MSB and AM[0] is the LSB. See Table 2.
99
ACLK
I
Input audio signal clock (128 fs). Synchronous to PCLK. In non-AES/EBU audio
modes, the serial audio data is sampled on both edges of ACLK.
NOTE: All unused inputs of the GS9023A should be connected to ground.
PIN DESCRIPTIONS (CONTINUED)
NUMBER
SYMBOL
TYPE
DESCRIPTION
相關(guān)PDF資料
PDF描述
GS9023 Embedded Audio CODEC
GS9023-CFY Aluminum Electrolytic Radial Leaded Bi-Polar Capacitor; Capacitance: 100uF; Voltage: 63V; Case Size: 12.5x20 mm; Packaging: Bulk
GS9024 Automatic Cable Equalizer
GS9024-CKB Automatic Cable Equalizer
GS9024-CTB Automatic Cable Equalizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS9023ACFYE3 制造商:Semtech Corporation 功能描述:Audio Codec 4ADC / 4DAC 24-Bit 100-Pin LQFP
GS9023B 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Embedded Audio CODEC
GS9023BCVE3 功能描述:IC AUDIO CODEC 100PIN TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
GS9023-CFY 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Embedded Audio CODEC
GS9024 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Automatic Cable Equalizer
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