參數(shù)資料
型號: GS9023ACFY
廠商: Gennum Corporation
元件分類: Codec
英文描述: GENLINX -TM II GS9023A Embedded Audio CODEC
中文描述: GENLINX -商標二GS9023A嵌入式音頻編解碼器
文件頁數(shù): 23/37頁
文件大小: 318K
代理商: GS9023ACFY
23 of 37
G
GENNUM CORPORATION
19795 - 6
2.2.6 Control Code Output
In the non-AES/EBU output formats, the V, U and C bits are
output separately from the audio data stream. The bits are
output respectively to the VFLA/B, UDA/B and CSA/B pins
according to the channel pair to which they belong and
change state on the rising edge of WCOUT. The SAFA/B
output pins are set to HIGH for one audio frame out of 192
frames to mark the start of a block. In the AES/EBU audio
output format, the respective pins are not used.
2.2.7 Detection of Audio Packets
The GS9023A can demultiplex up to four audio channels of
an audio group. The audio group (Audio packet data ID) for
each device is configured in “AD20ID[3:0]” of Host
Interface Register #3h. When the corresponding audio
packets are found on the active video line, the GS9023A
sets the respective “CHACT(4-1)” bits of Host Interface
Register #1h.
NOTE: When multiple audio groups are embedded in the
video stream, the status bits “CHACT(4-1)” are only valid if
the audio group being extracted immediately follows the
EAV. If the audio group does not immediately follow the EAV,
the device will still de-embed the audio correctly, however,
the “CHACT(4-1)” bits will be invalid.
If no corresponding audio packets are found on the active
video line, the “CHACT(4-1)” bits are set LOW.
By connecting four GS9023A devices in parallel, it is
possible to demultiplex up to 16 audio channels in a
component video signal as shown in Figure 15. On power
up, audio group 1 is selected by default.
NOTE: When more than two channels of audio are
embedded in an incoming audio data packet, audio
samples from channel 1 must be embedded in either the
1st or 2nd sample position after the start of the audio data
packet. Please refer to SMPTE 272M for details of the audio
data packet formatting.
Figure 15 Demultiplex Mode Parallel Architecture
S/P
PLL
CLK
54MHz
36MHz
27MHz
17.7MHz
14.3MHz
CPU
VIDEO INPUT
WITH 16 CH.
AUDIO DATA
DIN
AOUTA
AOUTB
WCOUT
PCLK
ACLK
DEMUX/MUX
DOUT
VDD
DIN
AOUTA
AOUTB
WCOUT
PCLK
ACLK
DEMUX/MUX
DOUT
VDD
DIN
AOUTA
AOUTB
WCOUT
PCLK
ACLK
DEMUX/MUX
DOUT
VDD
DIN
AOUTA
AOUTB
WCOUT
PCLK
ACLK
DEMUX/MUX
DOUT
VDD
10
10
10
10
10
10
10
10
AUDIO OUTPUT CH. 1/2
AUDIO OUTPUT CH. 3/4
WORD CLOCK #1
AUDIO OUTPUT CH. 5/6
AUDIO OUTPUT CH. 7/8
WORD CLOCK #2
AUDIO OUTPUT CH. 9/10
AUDIO OUTPUT CH. 11/12
WORD CLOCK #3
AUDIO OUTPUT CH. 13/14
AUDIO OUTPUT CH. 15/16
WORD CLOCK #4
128fs(6.144MHz)
GS9023A #1
GS9023A #2
GS9023A #3
GS9023A #4
Group DID No.
WORD CLOCK #1
WORD CLOCK #2
WORD CLOCK #3
WORD CLOCK #4
Time
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