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參數(shù)資料
| 型號(hào)： | GS832236AB-150VT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 CACHE SRAM, 7.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, FPBGA-119 |
| 文件頁(yè)數(shù)： | 5/36頁(yè) |
| 文件大?。?/td> | 790K |
| 代理商： | GS832236AB-150VT |
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First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
WR
R
W
R
X
CR
R
CW
CR
W
CW
W
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
GS832218/36A(B/D)-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00a 2/2011
13/36
2011, GSI Technology
Preliminary
Simplified State Diagram with G
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| GS8342D11BD-500IT | 4M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| GS8342D11BD-500 | 4M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| GS8342D11BD-550IT | 4M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| GS8342D37BD-300I | 1M X 36 QDR SRAM, 0.45 ns, PBGA165 |
| GS8342QT07BD-357 | 4M X 8 QDR SRAM, 0.45 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS832236AB-200 | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
| GS832236AB-200I | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
| GS832236AB-200IV | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS832236AB-200V | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS832236AB-225M | 制造商:GSI Technology 功能描述:2.5 OR 3.3V - Trays |
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