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參數(shù)資料
| 型號： | GS8170LW36AC |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 18Mb ヒ1x1Lp CMOS I/O Late Write SigmaRAM |
| 中文描述： | 35.7ヒ1x1Lp的CMOS的I / O后寫入SigmaRAM |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 765K |
| 代理商： | GS8170LW36AC |
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GS8170LW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
7/32
2003, GSI Technology
Two Byte Write Control Example with Late Write SigmaRAM
Special Functions
Burst Cycles
SRAMs provide an on-chip burst address generator that can be utilized, if desired, to simplify burst read or write implementations.
The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter
generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM
by driving the ADV pin low, into Load mode.
DA
DB
DE
DA
DC
F
/E
1
Write
B
C
D
ADV
ADV
Non-Write
Write
Write
CK
Address
A
E
Write
CQ
/BA
/BB
DQA0-DQA8
DQB0-DQB8
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相關代理商/技術參數(shù) |
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|---|---|
| GS8170LW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170LW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170LW36AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170LW36AGC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170LW36AGC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
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