參數(shù)資料
型號: GS8170LW36AC
廠商: GSI TECHNOLOGY
英文描述: 18Mb ヒ1x1Lp CMOS I/O Late Write SigmaRAM
中文描述: 35.7ヒ1x1Lp的CMOS的I / O后寫入SigmaRAM
文件頁數(shù): 6/32頁
文件大?。?/td> 765K
代理商: GS8170LW36AC
GS8170LW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
6/32
2003, GSI Technology
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
W
Ba
Bb
Bc
Bd
Read
H
X
X
X
X
Write Byte A
L
L
H
H
H
Write Byte B
L
H
L
H
H
Write Byte C
L
H
H
L
H
Write Byte D
L
H
H
H
L
Write all Bytes
L
L
L
L
L
Write Abort
L
H
H
H
H
SigmaRAM Late Write with Pipelined Read
Key
QD
QA
DC
CQ
Read
Read
C
D
E
ADV
Read
Deselect
Write
Hi-Z
F
Access
CK
Address
A
XX
/E
1
/W
DQ
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