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參數(shù)資料
| 型號： | GS8170LW36AC |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 18Mb ヒ1x1Lp CMOS I/O Late Write SigmaRAM |
| 中文描述： | 35.7ヒ1x1Lp的CMOS的I / O后寫入SigmaRAM |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 765K |
| 代理商： | GS8170LW36AC |
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GS8170LW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
5/32
2003, GSI Technology
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Single Data Rate Pipelined Read
F
D
Address
Read
CK
E
QC
QD
CQ
Read
Deselect
Read
Read
A
XX
C
Key
Hi-Z
Access
ADV
QA
/E
1
/W
DQ
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS8170LW36AC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays |
| GS8170LW36AGC-250 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170LW36AGC-250I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays |
| GS8170LW36AGC-350 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
| GS8170LW36AGC-350I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays |
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